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gem5/src/sim
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Ali Saidi c5fbbf376a Change everything to use the cached virtPort rather than created their own each time. 
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
2008-07-01 10:24:19 -04:00
..
arguments.cc Arguments: Get rid of duplicate code for the Arguments class in each architecture. 2007-08-01 16:59:14 -04:00
arguments.hh Arguments: Get rid of duplicate code for the Arguments class in each architecture. 2007-08-01 16:59:14 -04:00
async.cc Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
async.hh Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
byteswap.hh Make byteswap work correctly on Twin??_t types. 2007-03-07 17:46:04 +00:00
compile_info.cc add compile flags to m5 2008-06-15 20:56:35 -07:00
core.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
core.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
debug.cc Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
debug.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
eventq.cc Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
eventq.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
faults.cc put the flattenIndex stuff back in O3 AND put fatal() back in faults 2007-11-15 16:38:09 -05:00
faults.hh Address translation: Make the page table more flexible. 2007-08-26 20:33:57 -07:00
host.hh While I'm waiting for legion to run make m5 compile with a few more compilers 2007-01-27 15:38:04 -05:00
insttracer.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
InstTracer.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
main.cc String constant const-ness changes to placate g++ 4.2. 2007-10-31 18:04:22 -07:00
process.cc Add base ARM code to M5 2008-02-05 23:44:13 -05:00
process.hh Serialization: Fix serialization of file descriptors. Make sure open 2007-11-29 00:22:46 -05:00
Process.py Configs: Make using Simpoints easier with some config files that support them easily 2008-02-27 00:35:09 -05:00
process_impl.hh fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
pseudo_inst.cc Rename cycles() function to ticks() 2007-09-28 13:21:52 -04:00
pseudo_inst.hh add pseduo instruction support for sparc 2007-02-21 21:06:17 -05:00
root.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
Root.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
SConscript add compile flags to m5 2008-06-15 20:56:35 -07:00
serialize.cc Serialize: This shouldn't have been commited, I got a little bit carried away it seems. 2007-08-02 22:08:33 -04:00
serialize.hh Serialization: Provide array serialization methods that work on std::vector 2007-08-02 14:43:27 -04:00
sim_events.cc Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
sim_events.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
sim_exit.hh there are two main thrusts of this changeset. 2006-10-06 01:27:02 -04:00
sim_object.cc Add functional PrintReq command for memory-system debugging. 2008-01-02 12:20:15 -08:00
sim_object.hh SimObject: Add in missing includes of <string> and fix minor style problem. 2008-06-21 14:23:58 -04:00
sim_object_params.hh SimObject: Add in missing includes of <string> and fix minor style problem. 2008-06-21 14:23:58 -04:00
simulate.cc fix SIGUSR1 and SIGUSR2 by clearing the variables after 2007-04-18 08:04:46 -07:00
simulate.hh Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
startup.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
startup.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
stat_control.cc Get rid of the Statistics and Statreset ParamContexts, and 2007-02-17 22:52:32 -08:00
stat_control.hh Get rid of the Statistics and Statreset ParamContexts, and 2007-02-17 22:52:32 -08:00
stats.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
syscall_emul.cc Serialization: Fix serialization of file descriptors. Make sure open 2007-11-29 00:22:46 -05:00
syscall_emul.hh Serialization: Fix serialization of file descriptors. Make sure open 2007-11-29 00:22:46 -05:00
syscallreturn.hh Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed. 2006-12-05 01:55:02 -05:00
system.cc Add in files from merge-bare-iron, get them compiling in FS and SE mode 2007-11-13 16:58:16 -05:00
system.hh Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
System.py python: Improve support for python calling back to C++ member functions. 2007-08-02 22:50:02 -07:00
tlb.cc TLB: Make a TLB base class and put a virtual demapPage function in it. 2008-02-26 23:38:51 -05:00
tlb.hh TLB: Make a TLB base class and put a virtual demapPage function in it. 2008-02-26 23:38:51 -05:00
vptr.hh Change everything to use the cached virtPort rather than created their own each time. 2008-07-01 10:24:19 -04:00