sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/src/mem
History
Andreas Hansson b265d9925c Port: Align port names in C++ and Python 
This patch is a first step to align the port names used in the Python
world and the C++ world. Ultimately it serves to make the use of
config.json together with output from the simulation easier, including
post-processing of statistics.

Most notably, the CPU, cache, and bus is addressed in this patch, and
there might be other ports that should be updated accordingly. The
dash name separator has also been replaced with a "." which is what is
used to concatenate the names in python, and a separation is made
between the master and slave port in the bus.
2012-07-09 12:35:39 -04:00
..
cache Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
config Fixes to get prefetching working again. 2009-02-16 08:56:40 -08:00
protocol MOESI_hammer: tbe allocation and dependent wakeup fixes 2012-04-06 13:47:07 -07:00
ruby Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
slicc clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 2012-04-14 05:43:31 -04:00
abstract_mem.cc Mem: Fix a livelock resulting in LLSC/locked memory access implementation. 2012-06-29 11:19:05 -04:00
abstract_mem.hh Mem: add per-master stats to physmem 2012-06-05 01:23:11 -04:00
AbstractMemory.py MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
bridge.cc Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
bridge.hh Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
Bridge.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
bus.cc Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
bus.hh Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
Bus.py Bus: Make the default bus width 8 bytes instead of 64 2012-07-09 12:35:38 -04:00
coherent_bus.cc Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
coherent_bus.hh Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
comm_monitor.cc Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
comm_monitor.hh Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
CommMonitor.py MEM: Add the communication monitor 2012-05-09 04:37:45 -04:00
fs_translating_port_proxy.cc mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
fs_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
MemObject.py Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
noncoherent_bus.cc Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
noncoherent_bus.hh Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
packet.cc Packet: Cleaning up packet command and attribute 2012-05-23 09:18:04 -04:00
packet.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
packet_queue.cc MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
packet_queue.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
page_table.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
page_table.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
physical.cc MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
physical.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
port.cc Port: Add getAddrRanges to master port (asking slave port) 2012-07-09 12:35:33 -04:00
port.hh Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
port_proxy.cc MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
qport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
request.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
SConscript Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
se_translating_port_proxy.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
se_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
simple_mem.cc Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
simple_mem.hh Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
SimpleMemory.py MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
tport.cc mem: Delay deleting of incoming packets by one call. 2012-06-07 10:59:03 -04:00
tport.hh mem: Delay deleting of incoming packets by one call. 2012-06-07 10:59:03 -04:00