8caaac048a
This patch splits the existing buses into multiple layers. The non-coherent bus is split into a request and a response layer, and the coherent bus adds an additional layer for the snoop responses. The layer is modified to be templatised on the port type, such that the different layers can have retryLists with either master or slave ports. This patch also removes the dynamic cast from the retry, as previously promised when moving the recvRetry from the port base class to the master/slave port respectively. Overall, the split bus more closely reflects any modern on-chip bus and should be at step in the right direction. From this point, it would be reasonable straight forward to add separate layers (and thus contention points and arbitration) for each port and thus create a true crossbar. The regressions all produce the correct output, but have varying degrees of changes to their statistics. A separate patch will be pushed with the updates to the reference statistics.
215 lines
7 KiB
C++
215 lines
7 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Ali Saidi
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* Andreas Hansson
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* William Wang
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*/
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/**
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* @file
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* Declaration of a non-coherent bus.
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*/
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#ifndef __MEM_NONCOHERENT_BUS_HH__
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#define __MEM_NONCOHERENT_BUS_HH__
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#include "mem/bus.hh"
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#include "params/NoncoherentBus.hh"
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/**
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* A non-coherent bus connects a number of non-snooping masters and
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* slaves, and routes the request and response packets based on the
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* address. The request packets issued by the master connected to a
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* non-coherent bus could still snoop in caches attached to a coherent
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* bus, as is the case with the I/O bus and memory bus in most system
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* configurations. No snoops will, however, reach any master on the
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* non-coherent bus itself.
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*
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* The non-coherent bus can be used as a template for modelling PCI,
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* PCIe, and non-coherent AMBA and OCP buses, and is typically used
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* for the I/O buses.
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*/
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class NoncoherentBus : public BaseBus
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{
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protected:
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/**
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* Declare the two layers of this bus, one for requests and one
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* for responses.
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*/
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Layer<SlavePort> reqLayer;
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Layer<MasterPort> respLayer;
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/**
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* Declaration of the non-coherent bus slave port type, one will
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* be instantiated for each of the master ports connecting to the
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* bus.
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*/
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class NoncoherentBusSlavePort : public SlavePort
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{
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private:
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/** A reference to the bus to which this port belongs. */
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NoncoherentBus &bus;
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public:
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NoncoherentBusSlavePort(const std::string &_name,
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NoncoherentBus &_bus, PortID _id)
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: SlavePort(_name, &_bus, _id), bus(_bus)
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{ }
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protected:
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/**
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* When receiving a timing request, pass it to the bus.
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*/
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virtual bool recvTimingReq(PacketPtr pkt)
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{ return bus.recvTimingReq(pkt, id); }
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/**
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* When receiving an atomic request, pass it to the bus.
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*/
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virtual Tick recvAtomic(PacketPtr pkt)
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{ return bus.recvAtomic(pkt, id); }
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/**
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* When receiving a functional request, pass it to the bus.
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*/
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virtual void recvFunctional(PacketPtr pkt)
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{ bus.recvFunctional(pkt, id); }
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/**
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* When receiving a retry, pass it to the bus.
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*/
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virtual void recvRetry()
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{ panic("Bus slave ports always succeed and should never retry.\n"); }
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/**
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* Return the union of all adress ranges seen by this bus.
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*/
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virtual AddrRangeList getAddrRanges() const
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{ return bus.getAddrRanges(); }
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/**
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* Get the maximum block size as seen by the bus.
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*/
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virtual unsigned deviceBlockSize() const
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{ return bus.findBlockSize(); }
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};
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/**
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* Declaration of the bus master port type, one will be
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* instantiated for each of the slave ports connecting to the
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* bus.
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*/
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class NoncoherentBusMasterPort : public MasterPort
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{
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private:
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/** A reference to the bus to which this port belongs. */
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NoncoherentBus &bus;
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public:
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NoncoherentBusMasterPort(const std::string &_name,
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NoncoherentBus &_bus, PortID _id)
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: MasterPort(_name, &_bus, _id), bus(_bus)
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{ }
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protected:
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/**
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* When receiving a timing response, pass it to the bus.
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*/
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virtual bool recvTimingResp(PacketPtr pkt)
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{ return bus.recvTimingResp(pkt, id); }
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/** When reciving a range change from the peer port (at id),
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pass it to the bus. */
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virtual void recvRangeChange()
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{ bus.recvRangeChange(id); }
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/** When reciving a retry from the peer port (at id),
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pass it to the bus. */
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virtual void recvRetry()
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{ bus.recvRetry(); }
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/**
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* Get the maximum block size as seen by the bus.
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*/
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virtual unsigned deviceBlockSize() const
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{ return bus.findBlockSize(); }
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};
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/** Function called by the port when the bus is recieving a Timing
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request packet.*/
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virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
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/** Function called by the port when the bus is recieving a Timing
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response packet.*/
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virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
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/** Timing function called by port when it is once again able to process
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* requests. */
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void recvRetry();
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/** Function called by the port when the bus is recieving a Atomic
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transaction.*/
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Tick recvAtomic(PacketPtr pkt, PortID slave_port_id);
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/** Function called by the port when the bus is recieving a Functional
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transaction.*/
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void recvFunctional(PacketPtr pkt, PortID slave_port_id);
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public:
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NoncoherentBus(const NoncoherentBusParams *p);
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unsigned int drain(Event *de);
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};
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#endif //__MEM_NONCOHERENT_BUS_HH__
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