gem5/src/arch
Tony Gutierrez 0799600686 x86: fix issue with casting in Cvtf2i
UBSAN flags this operation because it detects that arg is being cast directly
to an unsigned type, argBits. this patch fixes this by first casting the
value to a signed int type, then reintrepreting the raw bits of the signed
int into argBits.
2016-11-21 15:35:56 -05:00
..
alpha alpha: Remove ALPHA tru64 support and associated tests 2016-11-17 04:54:14 -05:00
arm cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
generic cpu, arch: fix the type used for the request flags 2016-08-15 12:00:35 +01:00
hsail hsail,gpu-compute: fixes to appease clang++ 2016-10-26 22:48:45 -04:00
mips isa: Modify get/check interrupt routines 2016-07-21 17:19:15 +01:00
null cpu,isa,mem: Add per-thread wakeup logic 2015-09-30 11:14:19 -05:00
power isa: Modify get/check interrupt routines 2016-07-21 17:19:15 +01:00
sparc isa: Modify get/check interrupt routines 2016-07-21 17:19:15 +01:00
x86 x86: fix issue with casting in Cvtf2i 2016-11-21 15:35:56 -05:00
isa_parser.py cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF 2016-10-26 22:47:38 -04:00