sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

alpha: Remove ALPHA tru64 support and associated tests

Browse source 
No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.
This commit is contained in:
Andreas Hansson 2016-11-17 04:54:14 -05:00
parent 74249f80df
commit 6ed567d600
172 changed files with 0 additions and 52421 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/arch/alpha/AlphaSystem.py
View file

@ -54,9 +54,3 @@ class FreebsdAlphaSystem(AlphaSystem):
cxx_header = "arch/alpha/freebsd/system.hh"
system_type = 34
system_rev = 1 << 10
class Tru64AlphaSystem(AlphaSystem):
type = 'Tru64AlphaSystem'
cxx_header = "arch/alpha/tru64/system.hh"
system_type = 12
system_rev = 2<<1

3
src/arch/alpha/SConscript
View file

@ -52,9 +52,6 @@ if env['TARGET_ISA'] == 'alpha':
Source('stacktrace.cc')
Source('system.cc')
Source('tlb.cc')
Source('tru64/process.cc')
Source('tru64/system.cc')
Source('tru64/tru64.cc')
Source('utility.cc')
Source('vtophys.cc')

11
src/arch/alpha/kernel_stats.cc
View file

@ -39,7 +39,6 @@
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Context.hh"
#include "kern/tru64/tru64_syscalls.hh"
#include "sim/system.hh"
using namespace std;
@ -181,16 +180,6 @@ Statistics::callpal(int code, ThreadContext *tc)
return;
_callpal[code]++;
switch (code) {
case PAL::callsys: {
int number = tc->readIntReg(0);
if (SystemCalls<Tru64>::validSyscallNumber(number)) {
int cvtnum = SystemCalls<Tru64>::convert(number);
_syscall[cvtnum]++;
}
} break;
}
}
void

584
src/arch/alpha/tru64/process.cc
View file

@ -1,584 +0,0 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Ali Saidi
*/
#include "arch/alpha/tru64/process.hh"
#include "arch/alpha/tru64/tru64.hh"
#include "arch/alpha/isa_traits.hh"
#include "cpu/thread_context.hh"
#include "kern/tru64/tru64.hh"
#include "sim/byteswap.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
using namespace std;
using namespace AlphaISA;
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
ThreadContext *tc)
{
int index = 0;
TypedBufferArg<AlphaTru64::utsname> name(process->getSyscallArg(tc, index));
strcpy(name->sysname, "OSF1");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->release, "V5.1");
strcpy(name->version, "732");
strcpy(name->machine, "alpha");
name.copyOut(tc->getMemProxy());
return 0;
}
/// Target getsysyinfo() handler.
static SyscallReturn
getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
ThreadContext *tc)
{
int index = 0;
unsigned op = process->getSyscallArg(tc, index);
Addr bufPtr = process->getSyscallArg(tc, index);
unsigned nbytes = process->getSyscallArg(tc, index);
switch (op) {
case AlphaTru64::GSI_MAX_CPU: {
TypedBufferArg<uint32_t> max_cpu(bufPtr);
*max_cpu = htog((uint32_t)process->numCpus());
max_cpu.copyOut(tc->getMemProxy());
return 1;
}
case AlphaTru64::GSI_CPUS_IN_BOX: {
TypedBufferArg<uint32_t> cpus_in_box(bufPtr);
*cpus_in_box = htog((uint32_t)process->numCpus());
cpus_in_box.copyOut(tc->getMemProxy());
return 1;
}
case AlphaTru64::GSI_PHYSMEM: {
TypedBufferArg<uint64_t> physmem(bufPtr);
*physmem = htog((uint64_t)1024 * 1024); // physical memory in KB
physmem.copyOut(tc->getMemProxy());
return 1;
}
case AlphaTru64::GSI_CPU_INFO: {
TypedBufferArg<AlphaTru64::cpu_info> infop(bufPtr);
infop->current_cpu = htog(0);
infop->cpus_in_box = htog(process->numCpus());
infop->cpu_type = htog(57);
infop->ncpus = htog(process->numCpus());
uint64_t cpumask = (1 << process->numCpus()) - 1;
infop->cpus_present = infop->cpus_running = htog(cpumask);
infop->cpu_binding = htog(0);
infop->cpu_ex_binding = htog(0);
infop->mhz = htog(667);
infop.copyOut(tc->getMemProxy());
return 1;
}
case AlphaTru64::GSI_PROC_TYPE: {
TypedBufferArg<uint64_t> proc_type(bufPtr);
*proc_type = htog((uint64_t)11);
proc_type.copyOut(tc->getMemProxy());
return 1;
}
case AlphaTru64::GSI_PLATFORM_NAME: {
BufferArg bufArg(bufPtr, nbytes);
strncpy((char *)bufArg.bufferPtr(),
"COMPAQ Professional Workstation XP1000",
nbytes);
bufArg.copyOut(tc->getMemProxy());
return 1;
}
case AlphaTru64::GSI_CLK_TCK: {
TypedBufferArg<uint64_t> clk_hz(bufPtr);
*clk_hz = htog((uint64_t)1024);
clk_hz.copyOut(tc->getMemProxy());
return 1;
}
default:
warn("getsysinfo: unknown op %d\n", op);
break;
}
return 0;
}
/// Target setsysyinfo() handler.
static SyscallReturn
setsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
ThreadContext *tc)
{
int index = 0;
unsigned op = process->getSyscallArg(tc, index);
switch (op) {
case AlphaTru64::SSI_IEEE_FP_CONTROL:
warn("setsysinfo: ignoring ieee_set_fp_control() arg 0x%x\n",
process->getSyscallArg(tc, index));
break;
default:
warn("setsysinfo: unknown op %d\n", op);
break;
}
return 0;
}
/// Target table() handler.
static SyscallReturn
tableFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
ThreadContext *tc)
{
using namespace std;
int argIndex = 0;
int id = process->getSyscallArg(tc, argIndex); // table ID
int index = process->getSyscallArg(tc, argIndex); // index into table
Addr bufPtr = process->getSyscallArg(tc, argIndex);
// arg 2 is buffer pointer; type depends on table ID
int nel = process->getSyscallArg(tc, argIndex); // number of elements
int lel = process->getSyscallArg(tc, argIndex); // expected element size
switch (id) {
case AlphaTru64::TBL_SYSINFO: {
if (index != 0 || nel != 1 || lel != sizeof(Tru64::tbl_sysinfo))
return -EINVAL;
TypedBufferArg<Tru64::tbl_sysinfo> elp(bufPtr);
const int clk_hz = one_million;
elp->si_user = htog(curTick() / (SimClock::Frequency / clk_hz));
elp->si_nice = htog(0);
elp->si_sys = htog(0);
elp->si_idle = htog(0);
elp->wait = htog(0);
elp->si_hz = htog(clk_hz);
elp->si_phz = htog(clk_hz);
elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch?
elp->si_max_procs = htog(process->numCpus());
elp.copyOut(tc->getMemProxy());
return 0;
}
default:
cerr << "table(): id " << id << " unknown." << endl;
return -EINVAL;
}
}
SyscallDesc AlphaTru64Process::syscallDescs[] = {
/* 0 */ SyscallDesc("syscall (#0)", AlphaTru64::indirectSyscallFunc,
SyscallDesc::SuppressReturnValue),
/* 1 */ SyscallDesc("exit", exitFunc),
/* 2 */ SyscallDesc("fork", unimplementedFunc),
/* 3 */ SyscallDesc("read", readFunc),
/* 4 */ SyscallDesc("write", writeFunc),
/* 5 */ SyscallDesc("old_open", unimplementedFunc),
/* 6 */ SyscallDesc("close", closeFunc),
/* 7 */ SyscallDesc("wait4", unimplementedFunc),
/* 8 */ SyscallDesc("old_creat", unimplementedFunc),
/* 9 */ SyscallDesc("link", unimplementedFunc),
/* 10 */ SyscallDesc("unlink", unlinkFunc),
/* 11 */ SyscallDesc("execv", unimplementedFunc),
/* 12 */ SyscallDesc("chdir", unimplementedFunc),
/* 13 */ SyscallDesc("fchdir", unimplementedFunc),
/* 14 */ SyscallDesc("mknod", unimplementedFunc),
/* 15 */ SyscallDesc("chmod", unimplementedFunc),
/* 16 */ SyscallDesc("chown", unimplementedFunc),
/* 17 */ SyscallDesc("obreak", brkFunc),
/* 18 */ SyscallDesc("pre_F64_getfsstat", unimplementedFunc),
/* 19 */ SyscallDesc("lseek", lseekFunc),
/* 20 */ SyscallDesc("getpid", getpidPseudoFunc),
/* 21 */ SyscallDesc("mount", unimplementedFunc),
/* 22 */ SyscallDesc("unmount", unimplementedFunc),
/* 23 */ SyscallDesc("setuid", setuidFunc),
/* 24 */ SyscallDesc("getuid", getuidPseudoFunc),
/* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc),
/* 26 */ SyscallDesc("ptrace", unimplementedFunc),
/* 27 */ SyscallDesc("recvmsg", unimplementedFunc),
/* 28 */ SyscallDesc("sendmsg", unimplementedFunc),
/* 29 */ SyscallDesc("recvfrom", unimplementedFunc),
/* 30 */ SyscallDesc("accept", unimplementedFunc),
/* 31 */ SyscallDesc("getpeername", unimplementedFunc),
/* 32 */ SyscallDesc("getsockname", unimplementedFunc),
/* 33 */ SyscallDesc("access", unimplementedFunc),
/* 34 */ SyscallDesc("chflags", unimplementedFunc),
/* 35 */ SyscallDesc("fchflags", unimplementedFunc),
/* 36 */ SyscallDesc("sync", unimplementedFunc),
/* 37 */ SyscallDesc("kill", unimplementedFunc),
/* 38 */ SyscallDesc("old_stat", unimplementedFunc),
/* 39 */ SyscallDesc("setpgid", unimplementedFunc),
/* 40 */ SyscallDesc("old_lstat", unimplementedFunc),
/* 41 */ SyscallDesc("dup", unimplementedFunc),
/* 42 */ SyscallDesc("pipe", unimplementedFunc),
/* 43 */ SyscallDesc("set_program_attributes", unimplementedFunc),
/* 44 */ SyscallDesc("profil", unimplementedFunc),
/* 45 */ SyscallDesc("open", openFunc<AlphaTru64>),
/* 46 */ SyscallDesc("obsolete osigaction", unimplementedFunc),
/* 47 */ SyscallDesc("getgid", getgidPseudoFunc),
/* 48 */ SyscallDesc("sigprocmask", ignoreFunc),
/* 49 */ SyscallDesc("getlogin", unimplementedFunc),
/* 50 */ SyscallDesc("setlogin", unimplementedFunc),
/* 51 */ SyscallDesc("acct", unimplementedFunc),
/* 52 */ SyscallDesc("sigpending", unimplementedFunc),
/* 53 */ SyscallDesc("classcntl", unimplementedFunc),
/* 54 */ SyscallDesc("ioctl", ioctlFunc<AlphaTru64>),
/* 55 */ SyscallDesc("reboot", unimplementedFunc),
/* 56 */ SyscallDesc("revoke", unimplementedFunc),
/* 57 */ SyscallDesc("symlink", unimplementedFunc),
/* 58 */ SyscallDesc("readlink", readlinkFunc),
/* 59 */ SyscallDesc("execve", unimplementedFunc),
/* 60 */ SyscallDesc("umask", umaskFunc),
/* 61 */ SyscallDesc("chroot", unimplementedFunc),
/* 62 */ SyscallDesc("old_fstat", unimplementedFunc),
/* 63 */ SyscallDesc("getpgrp", unimplementedFunc),
/* 64 */ SyscallDesc("getpagesize", getpagesizeFunc),
/* 65 */ SyscallDesc("mremap", unimplementedFunc),
/* 66 */ SyscallDesc("vfork", unimplementedFunc),
/* 67 */ SyscallDesc("pre_F64_stat", statFunc<Tru64_PreF64>),
/* 68 */ SyscallDesc("pre_F64_lstat", lstatFunc<Tru64_PreF64>),
/* 69 */ SyscallDesc("sbrk", unimplementedFunc),
/* 70 */ SyscallDesc("sstk", unimplementedFunc),
/* 71 */ SyscallDesc("mmap", mmapFunc<AlphaTru64>),
/* 72 */ SyscallDesc("ovadvise", unimplementedFunc),
/* 73 */ SyscallDesc("munmap", munmapFunc),
/* 74 */ SyscallDesc("mprotect", ignoreFunc),
/* 75 */ SyscallDesc("madvise", unimplementedFunc),
/* 76 */ SyscallDesc("old_vhangup", unimplementedFunc),
/* 77 */ SyscallDesc("kmodcall", unimplementedFunc),
/* 78 */ SyscallDesc("mincore", unimplementedFunc),
/* 79 */ SyscallDesc("getgroups", unimplementedFunc),
/* 80 */ SyscallDesc("setgroups", unimplementedFunc),
/* 81 */ SyscallDesc("old_getpgrp", unimplementedFunc),
/* 82 */ SyscallDesc("setpgrp", unimplementedFunc),
/* 83 */ SyscallDesc("setitimer", unimplementedFunc),
/* 84 */ SyscallDesc("old_wait", unimplementedFunc),
/* 85 */ SyscallDesc("table", tableFunc),
/* 86 */ SyscallDesc("getitimer", unimplementedFunc),
/* 87 */ SyscallDesc("gethostname", gethostnameFunc),
/* 88 */ SyscallDesc("sethostname", unimplementedFunc),
/* 89 */ SyscallDesc("getdtablesize", unimplementedFunc),
/* 90 */ SyscallDesc("dup2", unimplementedFunc),
/* 91 */ SyscallDesc("pre_F64_fstat", fstatFunc<Tru64_PreF64>),
/* 92 */ SyscallDesc("fcntl", fcntlFunc),
/* 93 */ SyscallDesc("select", unimplementedFunc),
/* 94 */ SyscallDesc("poll", unimplementedFunc),
/* 95 */ SyscallDesc("fsync", unimplementedFunc),
/* 96 */ SyscallDesc("setpriority", unimplementedFunc),
/* 97 */ SyscallDesc("socket", unimplementedFunc),
/* 98 */ SyscallDesc("connect", unimplementedFunc),
/* 99 */ SyscallDesc("old_accept", unimplementedFunc),
/* 100 */ SyscallDesc("getpriority", unimplementedFunc),
/* 101 */ SyscallDesc("old_send", unimplementedFunc),
/* 102 */ SyscallDesc("old_recv", unimplementedFunc),
/* 103 */ SyscallDesc("sigreturn", AlphaTru64::sigreturnFunc,
SyscallDesc::SuppressReturnValue),
/* 104 */ SyscallDesc("bind", unimplementedFunc),
/* 105 */ SyscallDesc("setsockopt", unimplementedFunc),
/* 106 */ SyscallDesc("listen", unimplementedFunc),
/* 107 */ SyscallDesc("plock", unimplementedFunc),
/* 108 */ SyscallDesc("old_sigvec", unimplementedFunc),
/* 109 */ SyscallDesc("old_sigblock", unimplementedFunc),
/* 110 */ SyscallDesc("old_sigsetmask", unimplementedFunc),
/* 111 */ SyscallDesc("sigsuspend", unimplementedFunc),
/* 112 */ SyscallDesc("sigstack", ignoreFunc),
/* 113 */ SyscallDesc("old_recvmsg", unimplementedFunc),
/* 114 */ SyscallDesc("old_sendmsg", unimplementedFunc),
/* 115 */ SyscallDesc("obsolete vtrace", unimplementedFunc),
/* 116 */ SyscallDesc("gettimeofday", gettimeofdayFunc<AlphaTru64>),
/* 117 */ SyscallDesc("getrusage", getrusageFunc<AlphaTru64>),
/* 118 */ SyscallDesc("getsockopt", unimplementedFunc),
/* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc),
/* 120 */ SyscallDesc("readv", unimplementedFunc),
/* 121 */ SyscallDesc("writev", unimplementedFunc),
/* 122 */ SyscallDesc("settimeofday", unimplementedFunc),
/* 123 */ SyscallDesc("fchown", unimplementedFunc),
/* 124 */ SyscallDesc("fchmod", unimplementedFunc),
/* 125 */ SyscallDesc("old_recvfrom", unimplementedFunc),
/* 126 */ SyscallDesc("setreuid", unimplementedFunc),
/* 127 */ SyscallDesc("setregid", unimplementedFunc),
/* 128 */ SyscallDesc("rename", renameFunc),
/* 129 */ SyscallDesc("truncate", truncateFunc),
/* 130 */ SyscallDesc("ftruncate", ftruncateFunc),
/* 131 */ SyscallDesc("flock", unimplementedFunc),
/* 132 */ SyscallDesc("setgid", unimplementedFunc),
/* 133 */ SyscallDesc("sendto", unimplementedFunc),
/* 134 */ SyscallDesc("shutdown", unimplementedFunc),
/* 135 */ SyscallDesc("socketpair", unimplementedFunc),
/* 136 */ SyscallDesc("mkdir", mkdirFunc),
/* 137 */ SyscallDesc("rmdir", unimplementedFunc),
/* 138 */ SyscallDesc("utimes", unimplementedFunc),
/* 139 */ SyscallDesc("obsolete 4.2 sigreturn", unimplementedFunc),
/* 140 */ SyscallDesc("adjtime", unimplementedFunc),
/* 141 */ SyscallDesc("old_getpeername", unimplementedFunc),
/* 142 */ SyscallDesc("gethostid", unimplementedFunc),
/* 143 */ SyscallDesc("sethostid", unimplementedFunc),
/* 144 */ SyscallDesc("getrlimit", getrlimitFunc<AlphaTru64>),
/* 145 */ SyscallDesc("setrlimit", ignoreFunc),
/* 146 */ SyscallDesc("old_killpg", unimplementedFunc),
/* 147 */ SyscallDesc("setsid", unimplementedFunc),
/* 148 */ SyscallDesc("quotactl", unimplementedFunc),
/* 149 */ SyscallDesc("oldquota", unimplementedFunc),
/* 150 */ SyscallDesc("old_getsockname", unimplementedFunc),
/* 151 */ SyscallDesc("pread", unimplementedFunc),
/* 152 */ SyscallDesc("pwrite", unimplementedFunc),
/* 153 */ SyscallDesc("pid_block", unimplementedFunc),
/* 154 */ SyscallDesc("pid_unblock", unimplementedFunc),
/* 155 */ SyscallDesc("signal_urti", unimplementedFunc),
/* 156 */ SyscallDesc("sigaction", ignoreFunc),
/* 157 */ SyscallDesc("sigwaitprim", unimplementedFunc),
/* 158 */ SyscallDesc("nfssvc", unimplementedFunc),
/* 159 */ SyscallDesc("getdirentries", AlphaTru64::getdirentriesFunc),
/* 160 */ SyscallDesc("pre_F64_statfs", statfsFunc<Tru64_PreF64>),
/* 161 */ SyscallDesc("pre_F64_fstatfs", fstatfsFunc<Tru64_PreF64>),
/* 162 */ SyscallDesc("unknown #162", unimplementedFunc),
/* 163 */ SyscallDesc("async_daemon", unimplementedFunc),
/* 164 */ SyscallDesc("getfh", unimplementedFunc),
/* 165 */ SyscallDesc("getdomainname", unimplementedFunc),
/* 166 */ SyscallDesc("setdomainname", unimplementedFunc),
/* 167 */ SyscallDesc("unknown #167", unimplementedFunc),
/* 168 */ SyscallDesc("unknown #168", unimplementedFunc),
/* 169 */ SyscallDesc("exportfs", unimplementedFunc),
/* 170 */ SyscallDesc("unknown #170", unimplementedFunc),
/* 171 */ SyscallDesc("unknown #171", unimplementedFunc),
/* 172 */ SyscallDesc("unknown #172", unimplementedFunc),
/* 173 */ SyscallDesc("unknown #173", unimplementedFunc),
/* 174 */ SyscallDesc("unknown #174", unimplementedFunc),
/* 175 */ SyscallDesc("unknown #175", unimplementedFunc),
/* 176 */ SyscallDesc("unknown #176", unimplementedFunc),
/* 177 */ SyscallDesc("unknown #177", unimplementedFunc),
/* 178 */ SyscallDesc("unknown #178", unimplementedFunc),
/* 179 */ SyscallDesc("unknown #179", unimplementedFunc),
/* 180 */ SyscallDesc("unknown #180", unimplementedFunc),
/* 181 */ SyscallDesc("alt_plock", unimplementedFunc),
/* 182 */ SyscallDesc("unknown #182", unimplementedFunc),
/* 183 */ SyscallDesc("unknown #183", unimplementedFunc),
/* 184 */ SyscallDesc("getmnt", unimplementedFunc),
/* 185 */ SyscallDesc("unknown #185", unimplementedFunc),
/* 186 */ SyscallDesc("unknown #186", unimplementedFunc),
/* 187 */ SyscallDesc("alt_sigpending", unimplementedFunc),
/* 188 */ SyscallDesc("alt_setsid", unimplementedFunc),
/* 189 */ SyscallDesc("unknown #189", unimplementedFunc),
/* 190 */ SyscallDesc("unknown #190", unimplementedFunc),
/* 191 */ SyscallDesc("unknown #191", unimplementedFunc),
/* 192 */ SyscallDesc("unknown #192", unimplementedFunc),
/* 193 */ SyscallDesc("unknown #193", unimplementedFunc),
/* 194 */ SyscallDesc("unknown #194", unimplementedFunc),
/* 195 */ SyscallDesc("unknown #195", unimplementedFunc),
/* 196 */ SyscallDesc("unknown #196", unimplementedFunc),
/* 197 */ SyscallDesc("unknown #197", unimplementedFunc),
/* 198 */ SyscallDesc("unknown #198", unimplementedFunc),
/* 199 */ SyscallDesc("swapon", unimplementedFunc),
/* 200 */ SyscallDesc("msgctl", unimplementedFunc),
/* 201 */ SyscallDesc("msgget", unimplementedFunc),
/* 202 */ SyscallDesc("msgrcv", unimplementedFunc),
/* 203 */ SyscallDesc("msgsnd", unimplementedFunc),
/* 204 */ SyscallDesc("semctl", unimplementedFunc),
/* 205 */ SyscallDesc("semget", unimplementedFunc),
/* 206 */ SyscallDesc("semop", unimplementedFunc),
/* 207 */ SyscallDesc("uname", unameFunc),
/* 208 */ SyscallDesc("lchown", unimplementedFunc),
/* 209 */ SyscallDesc("shmat", unimplementedFunc),
/* 210 */ SyscallDesc("shmctl", unimplementedFunc),
/* 211 */ SyscallDesc("shmdt", unimplementedFunc),
/* 212 */ SyscallDesc("shmget", unimplementedFunc),
/* 213 */ SyscallDesc("mvalid", unimplementedFunc),
/* 214 */ SyscallDesc("getaddressconf", unimplementedFunc),
/* 215 */ SyscallDesc("msleep", unimplementedFunc),
/* 216 */ SyscallDesc("mwakeup", unimplementedFunc),
/* 217 */ SyscallDesc("msync", unimplementedFunc),
/* 218 */ SyscallDesc("signal", unimplementedFunc),
/* 219 */ SyscallDesc("utc_gettime", unimplementedFunc),
/* 220 */ SyscallDesc("utc_adjtime", unimplementedFunc),
/* 221 */ SyscallDesc("unknown #221", unimplementedFunc),
/* 222 */ SyscallDesc("security", unimplementedFunc),
/* 223 */ SyscallDesc("kloadcall", unimplementedFunc),
/* 224 */ SyscallDesc("stat", statFunc<Tru64_F64>),
/* 225 */ SyscallDesc("lstat", lstatFunc<Tru64_F64>),
/* 226 */ SyscallDesc("fstat", fstatFunc<Tru64_F64>),
/* 227 */ SyscallDesc("statfs", statfsFunc<Tru64_F64>),
/* 228 */ SyscallDesc("fstatfs", fstatfsFunc<Tru64_F64>),
/* 229 */ SyscallDesc("getfsstat", unimplementedFunc),
/* 230 */ SyscallDesc("gettimeofday64", unimplementedFunc),
/* 231 */ SyscallDesc("settimeofday64", unimplementedFunc),
/* 232 */ SyscallDesc("unknown #232", unimplementedFunc),
/* 233 */ SyscallDesc("getpgid", unimplementedFunc),
/* 234 */ SyscallDesc("getsid", unimplementedFunc),
/* 235 */ SyscallDesc("sigaltstack", ignoreFunc),
/* 236 */ SyscallDesc("waitid", unimplementedFunc),
/* 237 */ SyscallDesc("priocntlset", unimplementedFunc),
/* 238 */ SyscallDesc("sigsendset", unimplementedFunc),
/* 239 */ SyscallDesc("set_speculative", unimplementedFunc),
/* 240 */ SyscallDesc("msfs_syscall", unimplementedFunc),
/* 241 */ SyscallDesc("sysinfo", unimplementedFunc),
/* 242 */ SyscallDesc("uadmin", unimplementedFunc),
/* 243 */ SyscallDesc("fuser", unimplementedFunc),
/* 244 */ SyscallDesc("proplist_syscall", unimplementedFunc),
/* 245 */ SyscallDesc("ntp_adjtime", unimplementedFunc),
/* 246 */ SyscallDesc("ntp_gettime", unimplementedFunc),
/* 247 */ SyscallDesc("pathconf", unimplementedFunc),
/* 248 */ SyscallDesc("fpathconf", unimplementedFunc),
/* 249 */ SyscallDesc("sync2", unimplementedFunc),
/* 250 */ SyscallDesc("uswitch", unimplementedFunc),
/* 251 */ SyscallDesc("usleep_thread", unimplementedFunc),
/* 252 */ SyscallDesc("audcntl", unimplementedFunc),
/* 253 */ SyscallDesc("audgen", unimplementedFunc),
/* 254 */ SyscallDesc("sysfs", unimplementedFunc),
/* 255 */ SyscallDesc("subsys_info", unimplementedFunc),
/* 256 */ SyscallDesc("getsysinfo", getsysinfoFunc),
/* 257 */ SyscallDesc("setsysinfo", setsysinfoFunc),
/* 258 */ SyscallDesc("afs_syscall", unimplementedFunc),
/* 259 */ SyscallDesc("swapctl", unimplementedFunc),
/* 260 */ SyscallDesc("memcntl", unimplementedFunc),
/* 261 */ SyscallDesc("fdatasync", unimplementedFunc),
/* 262 */ SyscallDesc("oflock", unimplementedFunc),
/* 263 */ SyscallDesc("F64_readv", unimplementedFunc),
/* 264 */ SyscallDesc("F64_writev", unimplementedFunc),
/* 265 */ SyscallDesc("cdslxlate", unimplementedFunc),
/* 266 */ SyscallDesc("sendfile", unimplementedFunc),
};
SyscallDesc AlphaTru64Process::machSyscallDescs[] = {
/* 0 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 1 */ SyscallDesc("m5_mutex_lock", AlphaTru64::m5_mutex_lockFunc),
/* 2 */ SyscallDesc("m5_mutex_trylock", AlphaTru64::m5_mutex_trylockFunc),
/* 3 */ SyscallDesc("m5_mutex_unlock", AlphaTru64::m5_mutex_unlockFunc),
/* 4 */ SyscallDesc("m5_cond_signal", AlphaTru64::m5_cond_signalFunc),
/* 5 */ SyscallDesc("m5_cond_broadcast",
AlphaTru64::m5_cond_broadcastFunc),
/* 6 */ SyscallDesc("m5_cond_wait", AlphaTru64::m5_cond_waitFunc),
/* 7 */ SyscallDesc("m5_thread_exit", AlphaTru64::m5_thread_exitFunc),
/* 8 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 9 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 10 */ SyscallDesc("task_self", unimplementedFunc),
/* 11 */ SyscallDesc("thread_reply", unimplementedFunc),
/* 12 */ SyscallDesc("task_notify", unimplementedFunc),
/* 13 */ SyscallDesc("thread_self", unimplementedFunc),
/* 14 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 15 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 16 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 17 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 18 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 19 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 20 */ SyscallDesc("msg_send_trap", unimplementedFunc),
/* 21 */ SyscallDesc("msg_receive_trap", unimplementedFunc),
/* 22 */ SyscallDesc("msg_rpc_trap", unimplementedFunc),
/* 23 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 24 */ SyscallDesc("nxm_block", AlphaTru64::nxm_blockFunc),
/* 25 */ SyscallDesc("nxm_unblock", AlphaTru64::nxm_unblockFunc),
/* 26 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 27 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 28 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 29 */ SyscallDesc("nxm_thread_destroy", unimplementedFunc),
/* 30 */ SyscallDesc("lw_wire", unimplementedFunc),
/* 31 */ SyscallDesc("lw_unwire", unimplementedFunc),
/* 32 */ SyscallDesc("nxm_thread_create",
AlphaTru64::nxm_thread_createFunc),
/* 33 */ SyscallDesc("nxm_task_init", AlphaTru64::nxm_task_initFunc),
/* 34 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 35 */ SyscallDesc("nxm_idle", AlphaTru64::nxm_idleFunc),
/* 36 */ SyscallDesc("nxm_wakeup_idle", unimplementedFunc),
/* 37 */ SyscallDesc("nxm_set_pthid", unimplementedFunc),
/* 38 */ SyscallDesc("nxm_thread_kill", unimplementedFunc),
/* 39 */ SyscallDesc("nxm_thread_block", AlphaTru64::nxm_thread_blockFunc),
/* 40 */ SyscallDesc("nxm_thread_wakeup", unimplementedFunc),
/* 41 */ SyscallDesc("init_process", unimplementedFunc),
/* 42 */ SyscallDesc("nxm_get_binding", unimplementedFunc),
/* 43 */ SyscallDesc("map_fd", unimplementedFunc),
/* 44 */ SyscallDesc("nxm_resched", unimplementedFunc),
/* 45 */ SyscallDesc("nxm_set_cancel", unimplementedFunc),
/* 46 */ SyscallDesc("nxm_set_binding", unimplementedFunc),
/* 47 */ SyscallDesc("stack_create", AlphaTru64::stack_createFunc),
/* 48 */ SyscallDesc("nxm_get_state", unimplementedFunc),
/* 49 */ SyscallDesc("nxm_thread_suspend", unimplementedFunc),
/* 50 */ SyscallDesc("nxm_thread_resume", unimplementedFunc),
/* 51 */ SyscallDesc("nxm_signal_check", unimplementedFunc),
/* 52 */ SyscallDesc("htg_unix_syscall", unimplementedFunc),
/* 53 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 54 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 55 */ SyscallDesc("host_self", unimplementedFunc),
/* 56 */ SyscallDesc("host_priv_self", unimplementedFunc),
/* 57 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 58 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 59 */ SyscallDesc("swtch_pri", AlphaTru64::swtch_priFunc),
/* 60 */ SyscallDesc("swtch", unimplementedFunc),
/* 61 */ SyscallDesc("thread_switch", unimplementedFunc),
/* 62 */ SyscallDesc("semop_fast", unimplementedFunc),
/* 63 */ SyscallDesc("nxm_pshared_init", unimplementedFunc),
/* 64 */ SyscallDesc("nxm_pshared_block", unimplementedFunc),
/* 65 */ SyscallDesc("nxm_pshared_unblock", unimplementedFunc),
/* 66 */ SyscallDesc("nxm_pshared_destroy", unimplementedFunc),
/* 67 */ SyscallDesc("nxm_swtch_pri", AlphaTru64::swtch_priFunc),
/* 68 */ SyscallDesc("lw_syscall", unimplementedFunc),
/* 69 */ SyscallDesc("kern_invalid", unimplementedFunc),
/* 70 */ SyscallDesc("mach_sctimes_0", unimplementedFunc),
/* 71 */ SyscallDesc("mach_sctimes_1", unimplementedFunc),
/* 72 */ SyscallDesc("mach_sctimes_2", unimplementedFunc),
/* 73 */ SyscallDesc("mach_sctimes_3", unimplementedFunc),
/* 74 */ SyscallDesc("mach_sctimes_4", unimplementedFunc),
/* 75 */ SyscallDesc("mach_sctimes_5", unimplementedFunc),
/* 76 */ SyscallDesc("mach_sctimes_6", unimplementedFunc),
/* 77 */ SyscallDesc("mach_sctimes_7", unimplementedFunc),
/* 78 */ SyscallDesc("mach_sctimes_8", unimplementedFunc),
/* 79 */ SyscallDesc("mach_sctimes_9", unimplementedFunc),
/* 80 */ SyscallDesc("mach_sctimes_10", unimplementedFunc),
/* 81 */ SyscallDesc("mach_sctimes_11", unimplementedFunc),
/* 82 */ SyscallDesc("mach_sctimes_port_alloc_dealloc", unimplementedFunc)
};
SyscallDesc*
AlphaTru64Process::getDesc(int callnum)
{
if (callnum < -Num_Mach_Syscall_Descs || callnum > Num_Syscall_Descs)
return NULL;
if (callnum < 0)
return &machSyscallDescs[-callnum];
else
return &syscallDescs[callnum];
}
AlphaTru64Process::AlphaTru64Process(LiveProcessParams *params,
ObjectFile *objFile)
: AlphaLiveProcess(params, objFile),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)),
Num_Mach_Syscall_Descs(sizeof(machSyscallDescs) / sizeof(SyscallDesc))
{
}

60
src/arch/alpha/tru64/process.hh
View file

@ -1,60 +0,0 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
*/
#ifndef __ARCH_ALPHA_TRU64_PROCESS_HH__
#define __ARCH_ALPHA_TRU64_PROCESS_HH__
#include "arch/alpha/process.hh"
namespace AlphaISA {
/// A process with emulated Alpha Tru64 syscalls.
class AlphaTru64Process : public AlphaLiveProcess
{
public:
/// Constructor.
AlphaTru64Process(LiveProcessParams * params,
ObjectFile *objFile);
/// Array of syscall descriptors, indexed by call number.
static SyscallDesc syscallDescs[];
/// Array of mach syscall descriptors, indexed by call number.
static SyscallDesc machSyscallDescs[];
const int Num_Syscall_Descs;
const int Num_Mach_Syscall_Descs;
virtual SyscallDesc *getDesc(int callnum);
};
} // namespace AlphaISA
#endif // __ARCH_ALPHA_TRU64_PROCESS_HH__

92
src/arch/alpha/tru64/system.cc
View file

@ -1,92 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Lisa Hsu
*/
#include "arch/alpha/tru64/system.hh"
#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "kern/tru64/tru64_events.hh"
#include "kern/system_events.hh"
#include "mem/fs_translating_port_proxy.hh"
using namespace std;
Tru64AlphaSystem::Tru64AlphaSystem(Tru64AlphaSystem::Params *p)
: AlphaSystem(p)
{
Addr addr = 0;
if (kernelSymtab->findAddress("enable_async_printf", addr)) {
virtProxy.write(addr, (uint32_t)0);
}
#ifdef DEBUG
kernelPanicEvent = addKernelFuncEventOrPanic<BreakPCEvent>("panic");
#endif
badaddrEvent = addKernelFuncEventOrPanic<BadAddrEvent>("badaddr");
skipPowerStateEvent =
addKernelFuncEvent<SkipFuncEvent>("tl_v48_capture_power_state");
skipScavengeBootEvent =
addKernelFuncEvent<SkipFuncEvent>("pmap_scavenge_boot");
#if TRACING_ON
printfEvent = addKernelFuncEvent<PrintfEvent>("printf");
debugPrintfEvent = addKernelFuncEvent<DebugPrintfEvent>("m5printf");
debugPrintfrEvent = addKernelFuncEvent<DebugPrintfrEvent>("m5printfr");
dumpMbufEvent = addKernelFuncEvent<DumpMbufEvent>("m5_dump_mbuf");
#endif
}
Tru64AlphaSystem::~Tru64AlphaSystem()
{
#ifdef DEBUG
delete kernelPanicEvent;
#endif
delete badaddrEvent;
delete skipPowerStateEvent;
delete skipScavengeBootEvent;
#if TRACING_ON
delete printfEvent;
delete debugPrintfEvent;
delete debugPrintfrEvent;
delete dumpMbufEvent;
#endif
}
Tru64AlphaSystem *
Tru64AlphaSystemParams::create()
{
return new Tru64AlphaSystem(this);
}

76
src/arch/alpha/tru64/system.hh
View file

@ -1,76 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Lisa Hsu
*/
#ifndef __ARCH_ALPHA_TRU64_SYSTEM_HH__
#define __ARCH_ALPHA_TRU64_SYSTEM_HH__
#include "arch/alpha/system.hh"
#include "arch/isa_traits.hh"
#include "params/Tru64AlphaSystem.hh"
#include "sim/system.hh"
class ThreadContext;
class BreakPCEvent;
class BadAddrEvent;
class SkipFuncEvent;
class PrintfEvent;
class DebugPrintfEvent;
class DebugPrintfrEvent;
class DumpMbufEvent;
class AlphaArguments;
class Tru64AlphaSystem : public AlphaSystem
{
private:
#ifdef DEBUG
/** Event to halt the simulator if the kernel calls panic() */
BreakPCEvent *kernelPanicEvent;
#endif
BadAddrEvent *badaddrEvent;
SkipFuncEvent *skipPowerStateEvent;
SkipFuncEvent *skipScavengeBootEvent;
PrintfEvent *printfEvent;
DebugPrintfEvent *debugPrintfEvent;
DebugPrintfrEvent *debugPrintfrEvent;
DumpMbufEvent *dumpMbufEvent;
public:
typedef Tru64AlphaSystemParams Params;
Tru64AlphaSystem(Params *p);
~Tru64AlphaSystem();
static void Printf(AlphaArguments args);
static void DumpMbuf(AlphaArguments args);
};
#endif // __ARCH_ALPHA_TRU64_SYSTEM_HH__

94
src/arch/alpha/tru64/tru64.cc
View file

@ -1,94 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
*/
#include "arch/alpha/tru64/tru64.hh"
// open(2) flags translation table
SyscallFlagTransTable AlphaTru64::openFlagTable[] = {
#ifdef _MSC_VER
{ AlphaTru64::TGT_O_RDONLY, _O_RDONLY },
{ AlphaTru64::TGT_O_WRONLY, _O_WRONLY },
{ AlphaTru64::TGT_O_RDWR, _O_RDWR },
{ AlphaTru64::TGT_O_APPEND, _O_APPEND },
{ AlphaTru64::TGT_O_CREAT, _O_CREAT },
{ AlphaTru64::TGT_O_TRUNC, _O_TRUNC },
{ AlphaTru64::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK
{ AlphaTru64::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif
#ifdef _O_NOCTTY
{ AlphaTru64::TGT_O_NOCTTY, _O_NOCTTY },
#endif
#ifdef _O_SYNC
{ AlphaTru64::TGT_O_SYNC, _O_SYNC },
#endif
#else /* !_MSC_VER */
{ AlphaTru64::TGT_O_RDONLY, O_RDONLY },
{ AlphaTru64::TGT_O_WRONLY, O_WRONLY },
{ AlphaTru64::TGT_O_RDWR, O_RDWR },
{ AlphaTru64::TGT_O_APPEND, O_APPEND },
{ AlphaTru64::TGT_O_CREAT, O_CREAT },
{ AlphaTru64::TGT_O_TRUNC, O_TRUNC },
{ AlphaTru64::TGT_O_EXCL, O_EXCL },
{ AlphaTru64::TGT_O_NONBLOCK, O_NONBLOCK },
{ AlphaTru64::TGT_O_NOCTTY, O_NOCTTY },
#ifdef O_SYNC
{ AlphaTru64::TGT_O_SYNC, O_SYNC },
#endif
#endif /* _MSC_VER */
};
const int AlphaTru64::NUM_OPEN_FLAGS =
(sizeof(AlphaTru64::openFlagTable)/sizeof(AlphaTru64::openFlagTable[0]));
// mmap(2) flags translation table
SyscallFlagTransTable AlphaTru64::mmapFlagTable[] = {
{ TGT_MAP_SHARED, MAP_SHARED },
{ TGT_MAP_PRIVATE, MAP_PRIVATE },
{ TGT_MAP_32BIT, MAP_32BIT},
{ TGT_MAP_ANON, MAP_ANON },
{ TGT_MAP_DENYWRITE, MAP_DENYWRITE },
{ TGT_MAP_EXECUTABLE, MAP_EXECUTABLE },
{ TGT_MAP_FILE, MAP_FILE },
{ TGT_MAP_GROWSDOWN, MAP_GROWSDOWN },
{ TGT_MAP_HUGETLB, MAP_HUGETLB },
{ TGT_MAP_LOCKED, MAP_LOCKED },
{ TGT_MAP_NONBLOCK, MAP_NONBLOCK },
{ TGT_MAP_NORESERVE, MAP_NORESERVE },
{ TGT_MAP_POPULATE, MAP_POPULATE },
{ TGT_MAP_STACK, MAP_STACK },
{ TGT_MAP_ANONYMOUS, MAP_ANONYMOUS },
{ TGT_MAP_FIXED, MAP_FIXED },
};
const unsigned AlphaTru64::NUM_MMAP_FLAGS =
sizeof(AlphaTru64::mmapFlagTable) /
sizeof(AlphaTru64::mmapFlagTable[0]);

168
src/arch/alpha/tru64/tru64.hh
View file

@ -1,168 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
*/
#ifndef __ALPHA_ALPHA_TRU64_TRU64_HH__
#define __ALPHA_ALPHA_TRU64_TRU64_HH__
#include "kern/tru64/tru64.hh"
class AlphaTru64 : public Tru64
{
public:
/// This table maps the target open() flags to the corresponding
/// host open() flags.
static SyscallFlagTransTable openFlagTable[];
/// Number of entries in openFlagTable[].
static const int NUM_OPEN_FLAGS;
//@{
/// open(2) flag values.
static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY
static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY
static const int TGT_O_RDWR = 00000002; //!< O_RDWR
static const int TGT_O_NONBLOCK = 00000004; //!< O_NONBLOCK
static const int TGT_O_APPEND = 00000010; //!< O_APPEND
static const int TGT_O_CREAT = 00001000; //!< O_CREAT
static const int TGT_O_TRUNC = 00002000; //!< O_TRUNC
static const int TGT_O_EXCL = 00004000; //!< O_EXCL
static const int TGT_O_NOCTTY = 00010000; //!< O_NOCTTY
static const int TGT_O_SYNC = 00040000; //!< O_SYNC
static const int TGT_O_DRD = 00100000; //!< O_DRD
static const int TGT_O_DIRECTIO = 00200000; //!< O_DIRECTIO
static const int TGT_O_CACHE = 00400000; //!< O_CACHE
static const int TGT_O_DSYNC = 02000000; //!< O_DSYNC
static const int TGT_O_RSYNC = 04000000; //!< O_RSYNC
//@}
/// For mmap().
static SyscallFlagTransTable mmapFlagTable[];
static const unsigned TGT_MAP_SHARED = 0x00001;
static const unsigned TGT_MAP_PRIVATE = 0x00002;
static const unsigned TGT_MAP_32BIT = 0x00040;
static const unsigned TGT_MAP_ANON = 0x00020;
static const unsigned TGT_MAP_DENYWRITE = 0x00800;
static const unsigned TGT_MAP_EXECUTABLE = 0x01000;
static const unsigned TGT_MAP_FILE = 0x00000;
static const unsigned TGT_MAP_GROWSDOWN = 0x00100;
static const unsigned TGT_MAP_HUGETLB = 0x40000;
static const unsigned TGT_MAP_LOCKED = 0x02000;
static const unsigned TGT_MAP_NONBLOCK = 0x10000;
static const unsigned TGT_MAP_NORESERVE = 0x04000;
static const unsigned TGT_MAP_POPULATE = 0x08000;
static const unsigned TGT_MAP_STACK = 0x20000;
static const unsigned TGT_MAP_ANONYMOUS = 0x00020;
static const unsigned TGT_MAP_FIXED = 0x00010;
static const unsigned NUM_MMAP_FLAGS;
//@{
//@{
/// For getsysinfo().
static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name string
static const unsigned GSI_CPU_INFO = 59; //!< CPU information
static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
static const unsigned GSI_MAX_CPU = 30; //!< max # CPUs on machine
static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system
static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
//@}
//@{
/// For getrusage().
static const int TGT_RUSAGE_THREAD = 1;
static const int TGT_RUSAGE_SELF = 0;
static const int TGT_RUSAGE_CHILDREN = -1;
//@}
//@{
/// For setsysinfo().
static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control()
//@}
//@{
/// ioctl() command codes.
static const unsigned TGT_TIOCGETP = 0x40067408;
static const unsigned TGT_TIOCSETP = 0x80067409;
static const unsigned TGT_TIOCSETN = 0x8006740a;
static const unsigned TGT_TIOCSETC = 0x80067411;
static const unsigned TGT_TIOCGETC = 0x40067412;
static const unsigned TGT_FIONREAD = 0x4004667f;
static const unsigned TGT_TIOCISATTY = 0x2000745e;
static const unsigned TGT_TCGETS = 0x402c7413;
static const unsigned TGT_TCGETA = 0x40127417;
static const unsigned TGT_TCSETAW = 0x80147419; // 2.6.15 kernel
//@}
static bool
isTtyReq(unsigned req)
{
switch (req) {
case TGT_TIOCGETP:
case TGT_TIOCSETP:
case TGT_TIOCSETN:
case TGT_TIOCSETC:
case TGT_TIOCGETC:
case TGT_FIONREAD:
case TGT_TIOCISATTY:
case TGT_TCGETS:
case TGT_TCGETA:
case TGT_TCSETAW:
return true;
default:
return false;
}
}
//@{
/// For table().
static const int TBL_SYSINFO = 12;
//@}
/// Resource enumeration for getrlimit().
enum rlimit_resources {
TGT_RLIMIT_CPU = 0,
TGT_RLIMIT_FSIZE = 1,
TGT_RLIMIT_DATA = 2,
TGT_RLIMIT_STACK = 3,
TGT_RLIMIT_CORE = 4,
TGT_RLIMIT_RSS = 5,
TGT_RLIMIT_NOFILE = 6,
TGT_RLIMIT_AS = 7,
TGT_RLIMIT_VMEM = 7,
TGT_RLIMIT_NPROC = 8,
TGT_RLIMIT_MEMLOCK = 9,
TGT_RLIMIT_LOCKS = 10
};
};
#endif // __ALPHA_ALPHA_TRU64_TRU64_HH__

8
src/kern/SConscript
View file

@ -44,11 +44,3 @@ Source('system_events.cc')
DebugFlag('DebugPrintf')
DebugFlag('Printf')
if env['TARGET_ISA'] == 'alpha':
Source('tru64/dump_mbuf.cc')
Source('tru64/printf.cc')
Source('tru64/tru64_events.cc')
Source('tru64/tru64_syscalls.cc')
DebugFlag('BADADDR')

21
src/kern/kernel_stats.cc
View file

@ -34,9 +34,6 @@
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh"
#if THE_ISA == ALPHA_ISA
#include "kern/tru64/tru64_syscalls.hh"
#endif
#include "sim/system.hh"
using namespace std;
@ -92,24 +89,6 @@ Statistics::regStats(const string &_name)
;
_iplUsed = _iplGood / _iplCount;
#if THE_ISA == ALPHA_ISA
_syscall
.init(SystemCalls<Tru64>::Number)
.name(name() + ".syscall")
.desc("number of syscalls executed")
.flags(total | pdf | nozero | nonan)
;
#endif
//@todo This needs to get the names of syscalls from an appropriate place.
#if 0
for (int i = 0; i < SystemCalls<Tru64>::Number; ++i) {
const char *str = SystemCalls<Tru64>::name(i);
if (str) {
_syscall.subname(i, str);
}
}
#endif
}
void

5
src/kern/kernel_stats.hh
View file

@ -58,11 +58,6 @@ class Statistics : public Serializable
Stats::Vector _iplTicks;
Stats::Formula _iplUsed;
#if THE_ISA == ALPHA_ISA
Stats::Vector _syscall;
#endif
// Stats::Vector _faults;
private:
int iplLast;
Tick iplLastTick;

82
src/kern/tru64/dump_mbuf.cc
View file

@ -1,82 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#include <sys/types.h>
#include <algorithm>
#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "kern/tru64/dump_mbuf.hh"
#include "kern/tru64/mbuf.hh"
#include "sim/arguments.hh"
#include "sim/system.hh"
using namespace TheISA;
namespace tru64 {
void
DumpMbuf(Arguments args)
{
ThreadContext *tc = args.getThreadContext();
StringWrap name(tc->getSystemPtr()->name());
Addr addr = (Addr)args;
struct mbuf m;
CopyOut(tc, &m, addr, sizeof(m));
int count = m.m_pkthdr.len;
DPRINTFN("m=%#lx, m->m_pkthdr.len=%#d\n", addr, m.m_pkthdr.len);
while (count > 0) {
DPRINTFN("m=%#lx, m->m_data=%#lx, m->m_len=%d\n",
addr, m.m_data, m.m_len);
char *buffer = new char[m.m_len];
CopyOut(tc, buffer, m.m_data, m.m_len);
DDUMPN((uint8_t *)buffer, m.m_len);
delete [] buffer;
count -= m.m_len;
if (!m.m_next)
break;
CopyOut(tc, &m, m.m_next, sizeof(m));
}
}
} // namespace Tru64

40
src/kern/tru64/dump_mbuf.hh
View file

@ -1,40 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#ifndef __DUMP_MBUF_HH__
#define __DUMP_MBUF_HH__
#include "sim/arguments.hh"
namespace tru64 {
void DumpMbuf(Arguments args);
}
#endif // __DUMP_MBUF_HH__

100
src/kern/tru64/mbuf.hh
View file

@ -1,100 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#ifndef __MBUF_HH__
#define __MBUF_HH__
#include "arch/isa_traits.hh"
#include "base/types.hh"
namespace tru64 {
struct m_hdr {
Addr mh_next; // 0x00
Addr mh_nextpkt; // 0x08
Addr mh_data; // 0x10
int32_t mh_len; // 0x18
int32_t mh_type; // 0x1C
int32_t mh_flags; // 0x20
int32_t mh_pad0; // 0x24
Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
};
struct pkthdr {
int32_t len;
int32_t protocolSum;
Addr rcvif;
};
struct m_ext {
Addr ext_buf; // 0x00
Addr ext_free; // 0x08
uint32_t ext_size; // 0x10
uint32_t ext_pad0; // 0x14
Addr ext_arg; // 0x18
struct ext_refq {
Addr forw, back; // 0x20, 0x28
} ext_ref;
Addr uiomove_f; // 0x30
int32_t protocolSum; // 0x38
int32_t bytesSummed; // 0x3C
Addr checksum; // 0x40
};
struct mbuf {
struct m_hdr m_hdr;
union {
struct {
struct pkthdr MH_pkthdr;
union {
struct m_ext MH_ext;
char MH_databuf[1];
} MH_dat;
} MH;
char M_databuf[1];
} M_dat;
};
#define m_attr m_hdr.mh_attr
#define m_next m_hdr.mh_next
#define m_len m_hdr.mh_len
#define m_data m_hdr.mh_data
#define m_type m_hdr.mh_type
#define m_flags m_hdr.mh_flags
#define m_nextpkt m_hdr.mh_nextpkt
#define m_act m_nextpkt
#define m_pkthdr M_dat.MH.MH_pkthdr
#define m_ext M_dat.MH.MH_dat.MH_ext
#define m_pktdat M_dat.MH.MH_dat.MH_databuf
#define m_dat M_dat.M_databuf
}
#endif // __MBUF_HH__

272
src/kern/tru64/printf.cc
View file

@ -1,272 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#include <sys/types.h>
#include <algorithm>
#include "arch/vtophys.hh"
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "kern/tru64/printf.hh"
#include "sim/arguments.hh"
using namespace std;
namespace tru64 {
void
Printf(Arguments args)
{
std::ostream &out = Trace::output();
char *p = (char *)args++;
ios::fmtflags saved_flags = out.flags();
char old_fill = out.fill();
int old_precision = out.precision();
while (*p) {
switch (*p) {
case '%': {
bool more = true;
bool islong = false;
bool leftjustify = false;
bool format = false;
bool zero = false;
int width = 0;
while (more && *++p) {
switch (*p) {
case 'l':
case 'L':
islong = true;
break;
case '-':
leftjustify = true;
break;
case '#':
format = true;
break;
case '0':
if (width)
width *= 10;
else
zero = true;
break;
default:
if (*p >= '1' && *p <= '9')
width = 10 * width + *p - '0';
else
more = false;
break;
}
}
bool hexnum = false;
bool octal = false;
bool sign = false;
switch (*p) {
case 'X':
case 'x':
hexnum = true;
break;
case 'O':
case 'o':
octal = true;
break;
case 'D':
case 'd':
sign = true;
break;
case 'P':
format = true;
case 'p':
hexnum = true;
break;
}
switch (*p) {
case 'D':
case 'd':
case 'U':
case 'u':
case 'X':
case 'x':
case 'O':
case 'o':
case 'P':
case 'p': {
if (hexnum)
out << hex;
if (octal)
out << oct;
if (format) {
if (!zero)
out.setf(ios::showbase);
else {
if (hexnum) {
out << "0x";
width -= 2;
} else if (octal) {
out << "0";
width -= 1;
}
}
}
if (zero)
out.fill('0');
if (width > 0)
out.width(width);
if (leftjustify && !zero)
out.setf(ios::left);
if (sign) {
if (islong)
out << (int64_t)args;
else
out << (int32_t)args;
} else {
if (islong)
out << (uint64_t)args;
else
out << (uint32_t)args;
}
if (zero)
out.fill(' ');
if (width > 0)
out.width(0);
out << dec;
++args;
}
break;
case 's': {
const char *s = (char *)args;
if (!s)
s = "<NULL>";
if (width > 0)
out.width(width);
if (leftjustify)
out.setf(ios::left);
out << s;
++args;
}
break;
case 'C':
case 'c': {
uint64_t mask = (*p == 'C') ? 0xffL : 0x7fL;
uint64_t num;
int width;
if (islong) {
num = (uint64_t)args;
width = sizeof(uint64_t);
} else {
num = (uint32_t)args;
width = sizeof(uint32_t);
}
while (width-- > 0) {
char c = (char)(num & mask);
if (c)
out << c;
num >>= 8;
}
++args;
}
break;
case 'b': {
uint64_t n = (uint64_t)args++;
char *s = (char *)args++;
out << s << ": " << n;
}
break;
case 'n':
case 'N': {
args += 2;
#if 0
uint64_t n = (uint64_t)args++;
struct reg_values *rv = (struct reg_values *)args++;
#endif
}
break;
case 'r':
case 'R': {
args += 2;
#if 0
uint64_t n = (uint64_t)args++;
struct reg_desc *rd = (struct reg_desc *)args++;
#endif
}
break;
case '%':
out << '%';
break;
}
++p;
}
break;
case '\n':
out << endl;
++p;
break;
case '\r':
++p;
if (*p != '\n')
out << endl;
break;
default: {
size_t len = strcspn(p, "%\n\r\0");
out.write(p, len);
p += len;
}
}
}
out.flags(saved_flags);
out.fill(old_fill);
out.precision(old_precision);
}
} // namespace Tru64

40
src/kern/tru64/printf.hh
View file

@ -1,40 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#ifndef __PRINTF_HH__
#define __PRINTF_HH__
#include "sim/arguments.hh"
namespace tru64 {
void Printf(Arguments args);
}
#endif // __PRINTF_HH__

1222
src/kern/tru64/tru64.hh
View file

File diff suppressed because it is too large Load diff

114
src/kern/tru64/tru64_events.cc
View file

@ -1,114 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Lisa Hsu
*/
#include "arch/alpha/ev5.hh"
#include "arch/isa_traits.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/BADADDR.hh"
#include "debug/DebugPrintf.hh"
#include "debug/Printf.hh"
#include "kern/tru64/dump_mbuf.hh"
#include "kern/tru64/printf.hh"
#include "kern/tru64/tru64_events.hh"
#include "kern/system_events.hh"
#include "sim/arguments.hh"
#include "sim/system.hh"
using namespace TheISA;
//void SkipFuncEvent::process(ExecContext *tc);
void
BadAddrEvent::process(ThreadContext *tc)
{
// The following gross hack is the equivalent function to the
// annotation for vmunix::badaddr in:
// simos/simulation/apps/tcl/osf/tlaser.tcl
uint64_t a0 = tc->readIntReg(16);
bool found = false;
MasterPort &dataPort = tc->getCpuPtr()->getDataPort();
// get the address ranges of the connected slave port
AddrRangeList resp = dataPort.getAddrRanges();
for (const auto &iter : resp) {
if (iter.contains(K0Seg2Phys(a0) & PAddrImplMask))
found = true;
}
if (!IsK0Seg(a0) || found ) {
DPRINTF(BADADDR, "badaddr arg=%#x bad\n", a0);
tc->setIntReg(ReturnValueReg, 0x1);
SkipFuncEvent::process(tc);
} else {
DPRINTF(BADADDR, "badaddr arg=%#x good\n", a0);
}
}
void
PrintfEvent::process(ThreadContext *tc)
{
if (DTRACE(Printf)) {
StringWrap name(tc->getSystemPtr()->name());
DPRINTFN("");
Arguments args(tc);
tru64::Printf(args);
}
}
void
DebugPrintfEvent::process(ThreadContext *tc)
{
if (DTRACE(DebugPrintf)) {
if (!raw) {
StringWrap name(tc->getSystemPtr()->name());
DPRINTFN("");
}
Arguments args(tc);
tru64::Printf(args);
}
}
void
DumpMbufEvent::process(ThreadContext *tc)
{
if (DTRACE(DebugPrintf)) {
Arguments args(tc);
tru64::DumpMbuf(args);
}
}

86
src/kern/tru64/tru64_events.hh
View file

@ -1,86 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Lisa Hsu
*/
#ifndef __TRU64_EVENTS_HH__
#define __TRU64_EVENTS_HH__
#include <string>
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
class ThreadContext;
class BadAddrEvent : public SkipFuncEvent
{
public:
BadAddrEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: SkipFuncEvent(q, desc, addr) {}
virtual void process(ThreadContext *tc);
};
class PrintfEvent : public PCEvent
{
public:
PrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr) {}
virtual void process(ThreadContext *tc);
};
class DebugPrintfEvent : public PCEvent
{
private:
bool raw;
public:
DebugPrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr,
bool r = false)
: PCEvent(q, desc, addr), raw(r) {}
virtual void process(ThreadContext *tc);
};
class DebugPrintfrEvent : public DebugPrintfEvent
{
public:
DebugPrintfrEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: DebugPrintfEvent(q, desc, addr, true)
{}
};
class DumpMbufEvent : public PCEvent
{
public:
DumpMbufEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr) {}
virtual void process(ThreadContext *tc);
};
#endif // __TRU64_EVENTS_HH__

440
src/kern/tru64/tru64_syscalls.cc
View file

@ -1,440 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#include "kern/tru64/tru64_syscalls.hh"
namespace {
const char *
standard_strings[SystemCalls<Tru64>::StandardNumber] = {
"syscall", // 0
"exit", // 1
"fork", // 2
"read", // 3
"write", // 4
"old_open", // 5
"close", // 6
"wait4", // 7
"old_creat", // 8
"link", // 9
"unlink", // 10
"execv", // 11
"chdir", // 12
"fchdir", // 13
"mknod", // 14
"chmod", // 15
"chown", // 16
"obreak", // 17
"pre_F64_getfsstat", // 18
"lseek", // 19
"getpid", // 20
"mount", // 21
"unmount", // 22
"setuid", // 23
"getuid", // 24
"exec_with_loader", // 25
"ptrace", // 26
"recvmsg", // 27
"sendmsg", // 28
"recvfrom", // 29
"accept", // 30
"getpeername", // 31
"getsockname", // 32
"access", // 33
"chflags", // 34
"fchflags", // 35
"sync", // 36
"kill", // 37
"old_stat", // 38
"setpgid", // 39
"old_lstat", // 40
"dup", // 41
"pipe", // 42
"set_program_attributes", // 43
"profil", // 44
"open", // 45
"obsolete_osigaction", // 46
"getgid", // 47
"sigprocmask", // 48
"getlogin", // 49
"setlogin", // 50
"acct", // 51
"sigpending", // 52
"classcntl", // 53
"ioctl", // 54
"reboot", // 55
"revoke", // 56
"symlink", // 57
"readlink", // 58
"execve", // 59
"umask", // 60
"chroot", // 61
"old_fstat", // 62
"getpgrp", // 63
"getpagesize", // 64
"mremap", // 65
"vfork", // 66
"pre_F64_stat", // 67
"pre_F64_lstat", // 68
"sbrk", // 69
"sstk", // 70
"mmap", // 71
"ovadvise", // 72
"munmap", // 73
"mprotect", // 74
"madvise", // 75
"old_vhangup", // 76
"kmodcall", // 77
"mincore", // 78
"getgroups", // 79
"setgroups", // 80
"old_getpgrp", // 81
"setpgrp", // 82
"setitimer", // 83
"old_wait", // 84
"table", // 85
"getitimer", // 86
"gethostname", // 87
"sethostname", // 88
"getdtablesize", // 89
"dup2", // 90
"pre_F64_fstat", // 91
"fcntl", // 92
"select", // 93
"poll", // 94
"fsync", // 95
"setpriority", // 96
"socket", // 97
"connect", // 98
"old_accept", // 99
"getpriority", // 100
"old_send", // 101
"old_recv", // 102
"sigreturn", // 103
"bind", // 104
"setsockopt", // 105
"listen", // 106
"plock", // 107
"old_sigvec", // 108
"old_sigblock", // 109
"old_sigsetmask", // 110
"sigsuspend", // 111
"sigstack", // 112
"old_recvmsg", // 113
"old_sendmsg", // 114
"obsolete_vtrcae", // 115
"gettimeofday", // 116
"getrusage", // 117
"getsockopt", // 118
"numa_syscalls", // 119
"readv", // 120
"writev", // 121
"settimeofday", // 122
"fchown", // 123
"fchmod", // 124
"old_recvfrom", // 125
"setreuid", // 126
"setregid", // 127
"rename", // 128
"truncate", // 129
"ftruncate", // 130
"flock", // 131
"setgid", // 132
"sendto", // 133
"shutdown", // 134
"socketpair", // 135
"mkdir", // 136
"rmdir", // 137
"utimes", // 138
"obsolete_42_sigreturn", // 139
"adjtime", // 140
"old_getpeername", // 141
"gethostid", // 142
"sethostid", // 143
"getrlimit", // 144
"setrlimit", // 145
"old_killpg", // 146
"setsid", // 147
"quotactl", // 148
"oldquota", // 149
"old_getsockname", // 150
"pread", // 151
"pwrite", // 152
"pid_block", // 153
"pid_unblock", // 154
"signal_urti", // 155
"sigaction", // 156
"sigwaitprim", // 157
"nfssvc", // 158
"getdirentries", // 159
"pre_F64_statfs", // 160
"pre_F64_fstatfs", // 161
0, // 162
"async_daemon", // 163
"getfh", // 164
"getdomainname", // 165
"setdomainname", // 166
0, // 167
0, // 168
"exportfs", // 169
0, // 170
0, // 171
0, // 172
0, // 173
0, // 174
0, // 175
0, // 176
0, // 177
0, // 178
0, // 179
0, // 180
"alt_plock", // 181
0, // 182
0, // 183
"getmnt", // 184
0, // 185
0, // 186
"alt_sigpending", // 187
"alt_setsid", // 188
0, // 189
0, // 190
0, // 191
0, // 192
0, // 193
0, // 194
0, // 195
0, // 196
0, // 197
0, // 198
"swapon", // 199
"msgctl", // 200
"msgget", // 201
"msgrcv", // 202
"msgsnd", // 203
"semctl", // 204
"semget", // 205
"semop", // 206
"uname", // 207
"lchown", // 208
"shmat", // 209
"shmctl", // 210
"shmdt", // 211
"shmget", // 212
"mvalid", // 213
"getaddressconf", // 214
"msleep", // 215
"mwakeup", // 216
"msync", // 217
"signal", // 218
"utc_gettime", // 219
"utc_adjtime", // 220
0, // 221
"security", // 222
"kloadcall", // 223
"stat", // 224
"lstat", // 225
"fstat", // 226
"statfs", // 227
"fstatfs", // 228
"getfsstat", // 229
"gettimeofday64", // 230
"settimeofday64", // 231
0, // 232
"getpgid", // 233
"getsid", // 234
"sigaltstack", // 235
"waitid", // 236
"priocntlset", // 237
"sigsendset", // 238
"set_speculative", // 239
"msfs_syscall", // 240
"sysinfo", // 241
"uadmin", // 242
"fuser", // 243
"proplist_syscall", // 244
"ntp_adjtime", // 245
"ntp_gettime", // 246
"pathconf", // 247
"fpathconf", // 248
"sync2", // 249
"uswitch", // 250
"usleep_thread", // 251
"audcntl", // 252
"audgen", // 253
"sysfs", // 254
"subsys_info", // 255
"getsysinfo", // 256
"setsysinfo", // 257
"afs_syscall", // 258
"swapctl", // 259
"memcntl", // 260
"fdatasync", // 261
"oflock", // 262
"_F64_readv", // 263
"_F64_writev", // 264
"cdslxlate", // 265
"sendfile", // 266
};
const char *
mach_strings[SystemCalls<Tru64>::MachNumber] = {
0, // 0
0, // 1
0, // 2
0, // 3
0, // 4
0, // 5
0, // 6
0, // 7
0, // 8
0, // 9
"task_self", // 10
"thread_reply", // 11
"task_notify", // 12
"thread_self", // 13
0, // 14
0, // 15
0, // 16
0, // 17
0, // 18
0, // 19
"msg_send_trap", // 20
"msg_receive_trap", // 21
"msg_rpc_trap", // 22
0, // 23
"nxm_block", // 24
"nxm_unblock", // 25
0, // 26
0, // 27
0, // 28
"nxm_thread_destroy", // 29
"lw_wire", // 30
"lw_unwire", // 31
"nxm_thread_create", // 32
"nxm_task_init", // 33
0, // 34
"nxm_idle", // 35
"nxm_wakeup_idle", // 36
"nxm_set_pthid", // 37
"nxm_thread_kill", // 38
"nxm_thread_block", // 39
"nxm_thread_wakeup", // 40
"init_process", // 41
"nxm_get_binding", // 42
"map_fd", // 43
"nxm_resched", // 44
"nxm_set_cancel", // 45
"nxm_set_binding", // 46
"stack_create", // 47
"nxm_get_state", // 48
"nxm_thread_suspend", // 49
"nxm_thread_resume", // 50
"nxm_signal_check", // 51
"htg_unix_syscall", // 52
0, // 53
0, // 54
"host_self", // 55
"host_priv_self", // 56
0, // 57
0, // 58
"swtch_pri", // 59
"swtch", // 60
"thread_switch", // 61
"semop_fast", // 62
"nxm_pshared_init", // 63
"nxm_pshared_block", // 64
"nxm_pshared_unblock", // 65
"nxm_pshared_destroy", // 66
"nxm_swtch_pri", // 67
"lw_syscall", // 68
0, // 69
"mach_sctimes_0", // 70
"mach_sctimes_1", // 71
"mach_sctimes_2", // 72
"mach_sctimes_3", // 73
"mach_sctimes_4", // 74
"mach_sctimes_5", // 75
"mach_sctimes_6", // 76
"mach_sctimes_7", // 77
"mach_sctimes_8", // 78
"mach_sctimes_9", // 79
"mach_sctimes_10", // 80
"mach_sctimes_11", // 81
"mach_sctimes_port_alloc_dealloc", // 82
};
}
const char *
SystemCalls<Tru64>::name(int num)
{
if (num >= Number)
return 0;
else if (num >= StandardNumber)
return mach_strings[num - StandardNumber];
else if (num >= 0)
return standard_strings[num];
else if (num > -MachNumber)
return mach_strings[-num];
else
return 0;
}

361
src/kern/tru64/tru64_syscalls.hh
View file

@ -1,361 +0,0 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
*/
#ifndef __KERN_TRU64_TRU64_SYSCALLS_HH__
#define __KERN_TRU64_TRU64_SYSCALLS_HH__
#include "kern/tru64/tru64.hh"
template <class OS>
class SystemCalls;
template <>
class SystemCalls<Tru64>
{
public:
enum {
syscall = 0,
exit = 1,
fork = 2,
read = 3,
write = 4,
old_open = 5,
close = 6,
wait4 = 7,
old_creat = 8,
link = 9,
unlink = 10,
execv = 11,
chdir = 12,
fchdir = 13,
mknod = 14,
chmod = 15,
chown = 16,
obreak = 17,
pre_F64_getfsstat = 18,
lseek = 19,
getpid = 20,
mount = 21,
unmount = 22,
setuid = 23,
getuid = 24,
exec_with_loader = 25,
ptrace = 26,
recvmsg = 27,
sendmsg = 28,
recvfrom = 29,
accept = 30,
getpeername = 31,
getsockname = 32,
access = 33,
chflags = 34,
fchflags = 35,
sync = 36,
kill = 37,
old_stat = 38,
setpgid = 39,
old_lstat = 40,
dup = 41,
pipe = 42,
set_program_attributes = 43,
profil = 44,
open = 45,
obsolete_osigaction = 46,
getgid = 47,
sigprocmask = 48,
getlogin = 49,
setlogin = 50,
acct = 51,
sigpending = 52,
classcntl = 53,
ioctl = 54,
reboot = 55,
revoke = 56,
symlink = 57,
readlink = 58,
execve = 59,
umask = 60,
chroot = 61,
old_fstat = 62,
getpgrp = 63,
getpagesize = 64,
mremap = 65,
vfork = 66,
pre_F64_stat = 67,
pre_F64_lstat = 68,
sbrk = 69,
sstk = 70,
mmap = 71,
ovadvise = 72,
munmap = 73,
mprotect = 74,
madvise = 75,
old_vhangup = 76,
kmodcall = 77,
mincore = 78,
getgroups = 79,
setgroups = 80,
old_getpgrp = 81,
setpgrp = 82,
setitimer = 83,
old_wait = 84,
table = 85,
getitimer = 86,
gethostname = 87,
sethostname = 88,
getdtablesize = 89,
dup2 = 90,
pre_F64_fstat = 91,
fcntl = 92,
select = 93,
poll = 94,
fsync = 95,
setpriority = 96,
socket = 97,
connect = 98,
old_accept = 99,
getpriority = 100,
old_send = 101,
old_recv = 102,
sigreturn = 103,
bind = 104,
setsockopt = 105,
listen = 106,
plock = 107,
old_sigvec = 108,
old_sigblock = 109,
old_sigsetmask = 110,
sigsuspend = 111,
sigstack = 112,
old_recvmsg = 113,
old_sendmsg = 114,
obsolete_vtrcae = 115,
gettimeofday = 116,
getrusage = 117,
getsockopt = 118,
numa_syscalls = 119,
readv = 120,
writev = 121,
settimeofday = 122,
fchown = 123,
fchmod = 124,
old_recvfrom = 125,
setreuid = 126,
setregid = 127,
rename = 128,
truncate = 129,
ftruncate = 130,
flock = 131,
setgid = 132,
sendto = 133,
shutdown = 134,
socketpair = 135,
mkdir = 136,
rmdir = 137,
utimes = 138,
obsolete_42_sigreturn = 139,
adjtime = 140,
old_getpeername = 141,
gethostid = 142,
sethostid = 143,
getrlimit = 144,
setrlimit = 145,
old_killpg = 146,
setsid = 147,
quotactl = 148,
oldquota = 149,
old_getsockname = 150,
pread = 151,
pwrite = 152,
pid_block = 153,
pid_unblock = 154,
signal_urti = 155,
sigaction = 156,
sigwaitprim = 157,
nfssvc = 158,
getdirentries = 159,
pre_F64_statfs = 160,
pre_F64_fstatfs = 161,
async_daemon = 163,
getfh = 164,
getdomainname = 165,
setdomainname = 166,
exportfs = 169,
alt_plock = 181,
getmnt = 184,
alt_sigpending = 187,
alt_setsid = 188,
swapon = 199,
msgctl = 200,
msgget = 201,
msgrcv = 202,
msgsnd = 203,
semctl = 204,
semget = 205,
semop = 206,
uname = 207,
lchown = 208,
shmat = 209,
shmctl = 210,
shmdt = 211,
shmget = 212,
mvalid = 213,
getaddressconf = 214,
msleep = 215,
mwakeup = 216,
msync = 217,
signal = 218,
utc_gettime = 219,
utc_adjtime = 220,
security = 222,
kloadcall = 223,
stat = 224,
lstat = 225,
fstat = 226,
statfs = 227,
fstatfs = 228,
getfsstat = 229,
gettimeofday64 = 230,
settimeofday64 = 231,
getpgid = 233,
getsid = 234,
sigaltstack = 235,
waitid = 236,
priocntlset = 237,
sigsendset = 238,
set_speculative = 239,
msfs_syscall = 240,
sysinfo = 241,
uadmin = 242,
fuser = 243,
proplist_syscall = 244,
ntp_adjtime = 245,
ntp_gettime = 246,
pathconf = 247,
fpathconf = 248,
sync2 = 249,
uswitch = 250,
usleep_thread = 251,
audcntl = 252,
audgen = 253,
sysfs = 254,
subsys_info = 255,
getsysinfo = 256,
setsysinfo = 257,
afs_syscall = 258,
swapctl = 259,
memcntl = 260,
fdatasync = 261,
oflock = 262,
_F64_readv = 263,
_F64_writev = 264,
cdslxlate = 265,
sendfile = 266,
StandardNumber
};
enum {
task_self = 10,
thread_reply = 11,
task_notify = 12,
thread_self = 13,
msg_send_trap = 20,
msg_receive_trap = 21,
msg_rpc_trap = 22,
nxm_block = 24,
nxm_unblock = 25,
nxm_thread_destroy = 29,
lw_wire = 30,
lw_unwire = 31,
nxm_thread_create = 32,
nxm_task_init = 33,
nxm_idle = 35,
nxm_wakeup_idle = 36,
nxm_set_pthid = 37,
nxm_thread_kill = 38,
nxm_thread_block = 39,
nxm_thread_wakeup = 40,
init_process = 41,
nxm_get_binding = 42,
map_fd = 43,
nxm_resched = 44,
nxm_set_cancel = 45,
nxm_set_binding = 46,
stack_create = 47,
nxm_get_state = 48,
nxm_thread_suspend = 49,
nxm_thread_resume = 50,
nxm_signal_check = 51,
htg_unix_syscall = 52,
host_self = 55,
host_priv_self = 56,
swtch_pri = 59,
swtch = 60,
thread_switch = 61,
semop_fast = 62,
nxm_pshared_init = 63,
nxm_pshared_block = 64,
nxm_pshared_unblock = 65,
nxm_pshared_destroy = 66,
nxm_swtch_pri = 67,
lw_syscall = 68,
mach_sctimes_0 = 70,
mach_sctimes_1 = 71,
mach_sctimes_2 = 72,
mach_sctimes_3 = 73,
mach_sctimes_4 = 74,
mach_sctimes_5 = 75,
mach_sctimes_6 = 76,
mach_sctimes_7 = 77,
mach_sctimes_8 = 78,
mach_sctimes_9 = 79,
mach_sctimes_10 = 80,
mach_sctimes_11 = 81,
mach_sctimes_port_alloc_dealloc = 82,
MachNumber
};
static const int Number = StandardNumber + MachNumber;
static const char *name(int num);
static bool validSyscallNumber(int num) {
return -MachNumber < num && num < StandardNumber;
}
static int convert(int syscall_num) {
if (!validSyscallNumber(syscall_num))
return -1;
return syscall_num < 0 ? StandardNumber - syscall_num : syscall_num;
}
};
#endif // __KERN_TRU64_TRU64_SYSCALLS_HH__

5
src/sim/process.cc
View file

@ -70,7 +70,6 @@
#if THE_ISA == ALPHA_ISA
#include "arch/alpha/linux/process.hh"
#include "arch/alpha/tru64/process.hh"
#elif THE_ISA == SPARC_ISA
#include "arch/sparc/linux/process.hh"
#include "arch/sparc/solaris/process.hh"
@ -591,10 +590,6 @@ LiveProcess::create(LiveProcessParams * params)
fatal("Object file architecture does not match compiled ISA (Alpha).");
switch (objFile->getOpSys()) {
case ObjectFile::Tru64:
process = new AlphaTru64Process(params, objFile);
break;
case ObjectFile::UnknownOpSys:
warn("Unknown operating system; assuming Linux.");
// fall through

6
tests/long/se/20.parser/ref/alpha/tru64/NOTE
View file

@ -1,6 +0,0 @@
I removed the reference outputs for this program because it's taking
way too long... over an hour for simple-atomic and over 19 hrs for
o3-timing. We need to find a shorter input if we want to keep this
in the regressions.
Steve

877
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
View file

@ -1,877 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/parser
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=114600000000
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr
View file

@ -1,7 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

72
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
View file

@ -1,72 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 28069
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Reading the dictionary files: *************************************************
Welcome to the Link Parser -- Version 2.1
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
* I thought terrible after our discussion
* I wonder how much money have you earned
* Janet who is an expert on dogs helped me choose one
* she interviewed more programmers than was hired
* such flowers are found chiefly particularly in Europe
* the dogs some of which were very large ran after the man
* the man whom I play tennis is here
* there is going to be an important meeting January
* to pretend that our program is usable in its current form would be happy
* we're thinking about going to a movie this theater
* which dog you said you chased
- also invited to the meeting were several prominent scientists
- he ran home so quickly that his mother could hardly believe he had called from school
- so many people attended that they spilled over into several neighboring fields
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
: Grace may not be possible to fix the problem
any program as good as ours should be useful
biochemically , I think the experiment has a lot of problems
Fred has had five years of experience as a programmer
he is looking for another job
how did John do it
how many more people do you think will come
how much more spilled
I have more money than John has time
I made it clear that I was angry
I wonder how John did it
I wonder how much more quickly he ran
invite John and whoever else you want to invite
it is easier to ignore the problem than it is to solve it
many who initially supported Thomas later changed their minds
neither Mary nor Louise are coming to the party
she interviewed more programmers than were hired
telling Joe that Sue was coming to the party would create a real problem
the man with whom I play tennis is here
there is a dog in the park
this is not the man we know and love
we like to eat at restaurants , usually on weekends
what did John say he thought you should do
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 422342506500 because target called exit()

833
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,833 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.422343 # Number of seconds simulated
sim_ticks 422342506500 # Number of ticks simulated
final_tick 422342506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 474436 # Simulator instruction rate (inst/s)
host_op_rate 474436 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 327462122 # Simulator tick rate (ticks/s)
host_mem_usage 257604 # Number of bytes of host memory used
host_seconds 1289.74 # Real time elapsed on the host
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 156672 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24196288 # Number of bytes read from this memory
system.physmem.bytes_read::total 24352960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 156672 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 156672 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18839168 # Number of bytes written to this memory
system.physmem.bytes_written::total 18839168 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2448 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 378067 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380515 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 294362 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294362 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 370960 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 57290677 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 57661636 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 370960 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 370960 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 44606374 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 44606374 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 44606374 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 370960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 57290677 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 102268011 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 380515 # Number of read requests accepted
system.physmem.writeReqs 294362 # Number of write requests accepted
system.physmem.readBursts 380515 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 294362 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24331840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue
system.physmem.bytesWritten 18837824 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24352960 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18839168 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 23759 # Per bank write bursts
system.physmem.perBankRdBursts::1 23180 # Per bank write bursts
system.physmem.perBankRdBursts::2 23498 # Per bank write bursts
system.physmem.perBankRdBursts::3 24625 # Per bank write bursts
system.physmem.perBankRdBursts::4 25498 # Per bank write bursts
system.physmem.perBankRdBursts::5 23629 # Per bank write bursts
system.physmem.perBankRdBursts::6 23701 # Per bank write bursts
system.physmem.perBankRdBursts::7 23987 # Per bank write bursts
system.physmem.perBankRdBursts::8 23227 # Per bank write bursts
system.physmem.perBankRdBursts::9 24022 # Per bank write bursts
system.physmem.perBankRdBursts::10 24752 # Per bank write bursts
system.physmem.perBankRdBursts::11 22836 # Per bank write bursts
system.physmem.perBankRdBursts::12 23786 # Per bank write bursts
system.physmem.perBankRdBursts::13 24450 # Per bank write bursts
system.physmem.perBankRdBursts::14 22762 # Per bank write bursts
system.physmem.perBankRdBursts::15 22473 # Per bank write bursts
system.physmem.perBankWrBursts::0 17837 # Per bank write bursts
system.physmem.perBankWrBursts::1 17476 # Per bank write bursts
system.physmem.perBankWrBursts::2 17996 # Per bank write bursts
system.physmem.perBankWrBursts::3 18950 # Per bank write bursts
system.physmem.perBankWrBursts::4 19553 # Per bank write bursts
system.physmem.perBankWrBursts::5 18644 # Per bank write bursts
system.physmem.perBankWrBursts::6 18825 # Per bank write bursts
system.physmem.perBankWrBursts::7 18731 # Per bank write bursts
system.physmem.perBankWrBursts::8 18487 # Per bank write bursts
system.physmem.perBankWrBursts::9 18977 # Per bank write bursts
system.physmem.perBankWrBursts::10 19288 # Per bank write bursts
system.physmem.perBankWrBursts::11 18104 # Per bank write bursts
system.physmem.perBankWrBursts::12 18331 # Per bank write bursts
system.physmem.perBankWrBursts::13 18778 # Per bank write bursts
system.physmem.perBankWrBursts::14 17209 # Per bank write bursts
system.physmem.perBankWrBursts::15 17155 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 422342412500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 380515 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 294362 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 379040 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1139 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6849 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 17525 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17561 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 17561 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17567 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17580 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 138956 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 310.667780 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 185.031528 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 328.663803 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 47467 34.16% 34.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 38428 27.65% 61.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13549 9.75% 71.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 8124 5.85% 77.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5242 3.77% 81.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3828 2.75% 83.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3157 2.27% 86.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2628 1.89% 88.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16533 11.90% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 138956 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17561 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.649109 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 17.965863 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 233.199678 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 17556 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 2 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 17561 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17561 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.761061 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.733847 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.964147 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 10711 60.99% 60.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 371 2.11% 63.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 6450 36.73% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 26 0.15% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17561 # Writes before turning the bus around for reads
system.physmem.totQLat 8688901500 # Total ticks spent queuing
system.physmem.totMemAccLat 15817370250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1900925000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22854.40 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 41604.40 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 57.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 44.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 57.66 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 44.61 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.80 # Data bus utilization in percentage
system.physmem.busUtilRead 0.45 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing
system.physmem.readRowHits 314590 # Number of row buffer hits during reads
system.physmem.writeRowHits 220977 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.07 # Row buffer hit rate for writes
system.physmem.avgGap 625806.50 # Average gap between requests
system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 505526280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 268693590 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1370001780 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 772622640 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 11362849680.000002 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 8093551410 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 616183200 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 31552584270 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 13412815680 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 73287717855 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 141246410115 # Total energy per rank (pJ)
system.physmem_0.averagePower 334.435695 # Core power per rank (mW)
system.physmem_0.totalIdleTime 402979630750 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 931134000 # Time in different power states
system.physmem_0.memoryStateTime::REF 4824278000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 298856786250 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 34929182250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 13606935500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 69194190500 # Time in different power states
system.physmem_1.actEnergy 486640980 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 258644430 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1344519120 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 763837380 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 10801683360.000002 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 7884425820 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 575860800 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 29572982250 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 12813870240 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 74790220020 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 139297315230 # Total energy per rank (pJ)
system.physmem_1.averagePower 329.820729 # Core power per rank (mW)
system.physmem_1.totalIdleTime 403542198250 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 850086750 # Time in different power states
system.physmem_1.memoryStateTime::REF 4586322000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 305319724750 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 33369590750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 13363845750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 64852936500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 124433445 # Number of BP lookups
system.cpu.branchPred.condPredicted 87996604 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6213149 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 71713401 # Number of BTB lookups
system.cpu.branchPred.BTBHits 67452940 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.059045 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15161931 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1121038 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 7034 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 4431 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 2603 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 736 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 149830728 # DTB read hits
system.cpu.dtb.read_misses 559329 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 150390057 # DTB read accesses
system.cpu.dtb.write_hits 57603632 # DTB write hits
system.cpu.dtb.write_misses 71396 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 57675028 # DTB write accesses
system.cpu.dtb.data_hits 207434360 # DTB hits
system.cpu.dtb.data_misses 630725 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 208065085 # DTB accesses
system.cpu.itb.fetch_hits 227956774 # ITB hits
system.cpu.itb.fetch_misses 48 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 227956822 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 485 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 844685013 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 611901617 # Number of instructions committed
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
system.cpu.discardedOps 14840042 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.380426 # CPI: cycles per instruction
system.cpu.ipc 0.724414 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction
system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction
system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 66.61% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction
system.cpu.op_class_0::MemRead 146469180 23.94% 90.63% # Class of committed instruction
system.cpu.op_class_0::MemWrite 57213427 9.35% 99.98% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 96355 0.02% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 7556 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 611901617 # Class of committed instruction
system.cpu.tickCycles 746838140 # Number of cycles that the object actually ticked
system.cpu.idleCycles 97846873 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2535505 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.585414 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 203187430 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2539601 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 80.007619 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1692948500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.585414 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997946 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997946 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 827 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3149 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 415624517 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 415624517 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 147521210 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147521210 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 55666220 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 55666220 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 203187430 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 203187430 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 203187430 # number of overall hits
system.cpu.dcache.overall_hits::total 203187430 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1811214 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1811214 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1543814 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1543814 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3355028 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3355028 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3355028 # number of overall misses
system.cpu.dcache.overall_misses::total 3355028 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39457833000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 39457833000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 51431912500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 51431912500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 90889745500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 90889745500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 90889745500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 90889745500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 149332424 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 149332424 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 206542458 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 206542458 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 206542458 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 206542458 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012129 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012129 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016244 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016244 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016244 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016244 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21785.295940 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21785.295940 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33314.837474 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33314.837474 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 27090.607142 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27090.607142 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 2339286 # number of writebacks
system.cpu.dcache.writebacks::total 2339286 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46422 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 46422 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769005 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 769005 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 815427 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 815427 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 815427 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 815427 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764792 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1764792 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774809 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 774809 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2539601 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2539601 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2539601 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2539601 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36307875000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36307875000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25218661500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 25218661500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61526536500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 61526536500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61526536500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 61526536500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011818 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011818 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012296 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012296 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20573.458515 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20573.458515 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32548.229951 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32548.229951 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24226.851580 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24226.851580 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24226.851580 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24226.851580 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 3176 # number of replacements
system.cpu.icache.tags.tagsinuse 1116.241776 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 227951769 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5005 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 45544.808991 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1116.241776 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.545040 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.545040 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1592 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 455918553 # Number of tag accesses
system.cpu.icache.tags.data_accesses 455918553 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 227951769 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 227951769 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 227951769 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 227951769 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 227951769 # number of overall hits
system.cpu.icache.overall_hits::total 227951769 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5005 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5005 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5005 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5005 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5005 # number of overall misses
system.cpu.icache.overall_misses::total 5005 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293603500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 293603500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 293603500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 293603500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 293603500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 293603500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 227956774 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 227956774 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 227956774 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 227956774 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 227956774 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 227956774 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58662.037962 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 58662.037962 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58662.037962 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 58662.037962 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58662.037962 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 58662.037962 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 3176 # number of writebacks
system.cpu.icache.writebacks::total 3176 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5005 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 5005 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 5005 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 5005 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 5005 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 5005 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 288598500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 288598500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 288598500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 288598500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 288598500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 288598500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57662.037962 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57662.037962 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57662.037962 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 57662.037962 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57662.037962 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 57662.037962 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 348623 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30598.806406 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4701891 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 381391 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 12.328269 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 70474186000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 42.061592 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.646104 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 30397.098711 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.001284 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.927646 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.933801 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1626 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30708 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41047687 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41047687 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2339286 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2339286 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3176 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3176 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 571694 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 571694 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2557 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2557 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1589840 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1589840 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2557 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2161534 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2164091 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2557 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2161534 # number of overall hits
system.cpu.l2cache.overall_hits::total 2164091 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 206458 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206458 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2448 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2448 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 171609 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 171609 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2448 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 378067 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 380515 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2448 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 378067 # number of overall misses
system.cpu.l2cache.overall_misses::total 380515 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18097806000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 18097806000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 254224000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 254224000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16908659000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 16908659000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 254224000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 35006465000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 35260689000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 254224000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 35006465000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 35260689000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339286 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2339286 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 3176 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3176 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 778152 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 778152 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5005 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 5005 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761449 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1761449 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 5005 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2539601 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2544606 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 5005 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2539601 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2544606 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265318 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265318 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.489111 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.489111 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097425 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097425 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.489111 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.148869 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.149538 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.489111 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.148869 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.149538 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87658.535877 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87658.535877 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103849.673203 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103849.673203 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98530.141193 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98530.141193 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103849.673203 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92593.283730 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 92665.700432 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103849.673203 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92593.283730 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 92665.700432 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 294362 # number of writebacks
system.cpu.l2cache.writebacks::total 294362 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206458 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206458 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2448 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2448 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 171609 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 171609 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2448 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 378067 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 380515 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2448 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 378067 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 380515 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16033226000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16033226000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 229744000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 229744000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15192569000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15192569000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229744000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 31225795000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 31455539000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229744000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 31225795000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 31455539000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265318 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265318 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.489111 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097425 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097425 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.149538 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.149538 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77658.535877 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77658.535877 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93849.673203 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93849.673203 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88530.141193 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88530.141193 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5083287 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538681 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2446 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2446 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1766454 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2633648 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3176 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 250480 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 778152 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 778152 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5005 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761449 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13186 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614707 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7627893 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 523584 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312248768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 312772352 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348623 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 18839168 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 2893229 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.029064 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2890783 99.92% 99.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2446 0.08% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2893229 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4884105500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7507500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3809401500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 726697 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 346182 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 174057 # Transaction distribution
system.membus.trans_dist::WritebackDirty 294362 # Transaction distribution
system.membus.trans_dist::CleanEvict 51820 # Transaction distribution
system.membus.trans_dist::ReadExReq 206458 # Transaction distribution
system.membus.trans_dist::ReadExResp 206458 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 174057 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107212 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1107212 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43192128 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 380515 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 380515 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 380515 # Request fanout histogram
system.membus.reqLayer0.occupancy 2021742500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 2013933750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

877
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
View file

@ -1,877 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

53
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr
View file

@ -1,53 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(1, ...)

17
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
View file

@ -1,17 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 28070
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.233333
Exiting @ tick 233641094500 because target called exit()

794
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,794 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.233641 # Number of seconds simulated
sim_ticks 233641094500 # Number of ticks simulated
final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 449379 # Simulator instruction rate (inst/s)
host_op_rate 449379 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 263362780 # Simulator tick rate (ticks/s)
host_mem_usage 260228 # Number of bytes of host memory used
host_seconds 887.15 # Real time elapsed on the host
sim_insts 398664651 # Number of instructions simulated
sim_ops 398664651 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7873 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 548 # Per bank write bursts
system.physmem.perBankRdBursts::1 675 # Per bank write bursts
system.physmem.perBankRdBursts::2 473 # Per bank write bursts
system.physmem.perBankRdBursts::3 633 # Per bank write bursts
system.physmem.perBankRdBursts::4 475 # Per bank write bursts
system.physmem.perBankRdBursts::5 477 # Per bank write bursts
system.physmem.perBankRdBursts::6 563 # Per bank write bursts
system.physmem.perBankRdBursts::7 560 # Per bank write bursts
system.physmem.perBankRdBursts::8 471 # Per bank write bursts
system.physmem.perBankRdBursts::9 437 # Per bank write bursts
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
system.physmem.perBankRdBursts::11 323 # Per bank write bursts
system.physmem.perBankRdBursts::12 430 # Per bank write bursts
system.physmem.perBankRdBursts::13 556 # Per bank write bursts
system.physmem.perBankRdBursts::14 473 # Per bank write bursts
system.physmem.perBankRdBursts::15 425 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 233641000500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7873 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation
system.physmem.totQLat 179319500 # Total ticks spent queuing
system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6337 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 29676235.30 # Average gap between requests
system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ)
system.physmem_0.averagePower 243.486327 # Core power per rank (mW)
system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states
system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states
system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ)
system.physmem_1.averagePower 242.981892 # Core power per rank (mW)
system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states
system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 45912950 # Number of BP lookups
system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups
system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 95338456 # DTB read hits
system.cpu.dtb.read_misses 116 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 95338572 # DTB read accesses
system.cpu.dtb.write_hits 73578378 # DTB write hits
system.cpu.dtb.write_misses 847 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73579225 # DTB write accesses
system.cpu.dtb.data_hits 168916834 # DTB hits
system.cpu.dtb.data_misses 963 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168917797 # DTB accesses
system.cpu.itb.fetch_hits 96959253 # ITB hits
system.cpu.itb.fetch_misses 1239 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 96960492 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 467282189 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664651 # Number of instructions committed
system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.172118 # CPI: cycles per instruction
system.cpu.ipc 0.853156 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction
system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.op_class_0::MemRead 46072315 11.56% 69.35% # Class of committed instruction
system.cpu.op_class_0::MemWrite 30396984 7.62% 76.97% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 48682195 12.21% 89.18% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 43123780 10.82% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 398664651 # Class of committed instruction
system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked
system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 771 # number of replacements
system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits
system.cpu.dcache.overall_hits::total 167817015 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses
system.cpu.dcache.overall_misses::total 6994 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
system.cpu.dcache.writebacks::total 654 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86354000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 3194 # number of replacements
system.cpu.icache.tags.tagsinuse 1919.615846 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 96954081 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5172 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18745.955336 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.615846 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.937312 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.937312 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 193923678 # Number of tag accesses
system.cpu.icache.tags.data_accesses 193923678 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 96954081 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 96954081 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 96954081 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 96954081 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 96954081 # number of overall hits
system.cpu.icache.overall_hits::total 96954081 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5172 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5172 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5172 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5172 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5172 # number of overall misses
system.cpu.icache.overall_misses::total 5172 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 373067500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 373067500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 373067500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 373067500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 373067500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 373067500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 96959253 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 96959253 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 96959253 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 96959253 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 96959253 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 96959253 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72132.153906 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72132.153906 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72132.153906 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72132.153906 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 3194 # number of writebacks
system.cpu.icache.writebacks::total 3194 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5172 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 5172 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 5172 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 5172 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 5172 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 5172 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 367895500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 367895500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 367895500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 367895500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 367895500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 367895500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71132.153906 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71132.153906 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 7128.397001 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5429 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.689572 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.799627 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.597374 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104120 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113422 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.217541 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7186 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 114289 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 114289 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3194 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3194 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1277 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1277 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1277 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1464 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1277 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits
system.cpu.l2cache.overall_hits::total 1464 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3895 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3895 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
system.cpu.l2cache.overall_misses::total 7873 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 298441000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 298441000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 346727500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 346727500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 83414000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 83414000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 346727500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 381855000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 728582500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 346727500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 381855000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 728582500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 3194 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3194 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5172 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 5172 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 5172 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9337 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 5172 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9337 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753094 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753094 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753094 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.843204 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753094 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.843204 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95135.798534 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95135.798534 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99184.304400 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 92541.915407 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3895 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3895 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 267071000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 267071000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307777500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307777500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 75004000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 75004000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307777500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 342075000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 649852500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307777500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 342075000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 649852500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753094 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843204 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843204 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85135.798534 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85135.798534 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79018.613607 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79018.613607 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89184.304400 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89184.304400 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4736 # Transaction distribution
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 4736 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 7873 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7873 # Request fanout histogram
system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

825
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,825 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

53
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,53 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(1, ...)

17
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -1,17 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:44
gem5 executing on e108600-lin, pid 28057
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.050000
Exiting @ tick 64255452000 because target called exit()

1059
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

366
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -1,366 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

52
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,52 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(1, ...)

17
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -1,17 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51
gem5 started Jul 21 2016 14:09:28
gem5 executing on e108600-lin, pid 4302
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.566667
Exiting @ tick 567385356500 because target called exit()

555
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,555 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.567393 # Number of seconds simulated
sim_ticks 567392530500 # Number of ticks simulated
final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1833225 # Simulator instruction rate (inst/s)
host_op_rate 1833225 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2609105944 # Simulator tick rate (ticks/s)
host_mem_usage 258692 # Number of bytes of host memory used
host_seconds 217.47 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754490 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754511 # DTB read accesses
system.cpu.dtb.write_hits 73520730 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520765 # DTB write accesses
system.cpu.dtb.data_hits 168275220 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275276 # DTB accesses
system.cpu.itb.fetch_hits 398664666 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664839 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1134785061 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664609 # Number of instructions committed
system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
system.cpu.num_int_insts 316365921 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
system.cpu.num_mem_refs 168275276 # number of memory refs
system.cpu.num_load_insts 94754511 # Number of load instructions
system.cpu.num_store_insts 73520765 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1134785061 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 44587535 # Number of branches fetched
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction
system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction
system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
system.cpu.op_class::MemRead 46072316 11.56% 69.35% # Class of executed instruction
system.cpu.op_class::MemWrite 30396985 7.62% 76.97% # Class of executed instruction
system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 398664665 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 764 # number of replacements
system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1769 # number of replacements
system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
system.cpu.icache.overall_hits::total 398660993 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
system.cpu.icache.overall_misses::total 3673 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1769 # number of writebacks
system.cpu.icache.writebacks::total 1769 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
system.cpu.l2cache.overall_hits::total 651 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 7174 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7174 # Request fanout histogram
system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

877
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
View file

@ -1,877 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

8
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr
View file

@ -1,8 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)
warn: ignoring syscall sigprocmask(1, ...)

653
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
View file

@ -1,653 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:44
gem5 executing on e108600-lin, pid 28059
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
634000: 545393176
633000: 3107247613
632000: 897887463
631000: 806367477
630000: 1682157095
629000: 1188376072
628000: 4076707785
627000: 3521684454
626000: 3144526095
625000: 1399223384
624000: 3380494826
623000: 4086509498
622000: 1473819475
621000: 638751284
620000: 3149483163
619000: 1489851375
618000: 1447059134
617000: 136329498
616000: 1288452788
615000: 3949816816
614000: 318984246
613000: 1019963195
612000: 2875280299
611000: 2997394777
610000: 4014932807
609000: 2291235006
608000: 355450951
607000: 201970399
606000: 3626124461
605000: 2207253273
604000: 2243886712
603000: 46791684
602000: 3176322294
601000: 1120582847
600000: 411705454
599000: 3162380308
598000: 2732375303
597000: 1376844609
596000: 3003023122
595000: 3869968535
594000: 1327286554
593000: 160655029
592000: 2038558826
591000: 3948772976
590000: 439262378
589000: 329537197
588000: 3678661972
587000: 4240182727
586000: 2283602206
585000: 1129811410
584000: 2831949168
583000: 1224559023
582000: 3161562107
581000: 2695467835
580000: 1234192577
579000: 1974816198
578000: 449576701
577000: 1424873035
576000: 2370444290
575000: 1743089134
574000: 2624046998
573000: 2071148441
572000: 2449219691
571000: 3774476172
570000: 1111630327
569000: 121721805
568000: 2981212266
567000: 3811833647
566000: 3676851843
565000: 1766252334
564000: 1622887950
563000: 1684409857
562000: 1686489387
561000: 610219569
560000: 2705092362
559000: 108031723
558000: 1316736987
557000: 2434129258
556000: 1411819652
555000: 1173886179
554000: 3044539233
553000: 151590417
552000: 3759426289
551000: 3451520306
550000: 294242855
549000: 890241051
548000: 876385779
547000: 119864600
546000: 3065674956
545000: 1670853168
544000: 997261561
543000: 660227344
542000: 3132294889
541000: 521956271
540000: 1133928405
539000: 3838154786
538000: 58624572
537000: 3544030439
536000: 432804999
535000: 1021857051
534000: 2644812356
533000: 773094580
532000: 901027171
531000: 3976696839
530000: 4167278216
529000: 504481120
528000: 320399857
527000: 638048690
526000: 3348998474
525000: 2660662065
524000: 2641437803
523000: 626927006
522000: 4063917554
521000: 3212249308
520000: 2561025301
519000: 1078140141
518000: 653939181
517000: 2154098204
516000: 3773089676
515000: 2568381435
514000: 3838886937
513000: 941125346
512000: 1318900410
511000: 297013287
510000: 241723934
509000: 1835499795
508000: 2309451230
507000: 1174814430
506000: 3615943386
505000: 51034971
504000: 3950453295
503000: 4186097241
502000: 327518343
501000: 3052462710
500000: 1586937404
499000: 2169094819
498000: 3613195151
497000: 817359591
496000: 1470916579
495000: 2091261583
494000: 2080080890
493000: 1772858697
492000: 2085609872
491000: 3280632925
490000: 1689322569
489000: 2947406469
488000: 765163324
487000: 3122594732
486000: 3385418480
485000: 1712345567
484000: 3675825158
483000: 1558929764
482000: 2672493410
481000: 3822528440
480000: 3741769935
479000: 2794026235
478000: 2541364185
477000: 3964482316
476000: 1202478165
475000: 4027617791
474000: 1905026738
473000: 2573787636
472000: 1170529797
471000: 2272525618
470000: 820833429
469000: 3219769529
468000: 2121197441
467000: 269331764
466000: 3038487237
465000: 2462675338
464000: 2703163101
463000: 547052037
462000: 3454526671
461000: 2124641794
460000: 1043737466
459000: 1785834964
458000: 3312335313
457000: 1213835042
456000: 3099430685
455000: 3003350806
454000: 3646781335
453000: 1474165966
452000: 705795987
451000: 2723908407
450000: 1323056304
449000: 1157256530
448000: 4077983523
447000: 3189085703
446000: 2241002747
445000: 3229050072
444000: 3500150226
443000: 1290722604
442000: 1866107725
441000: 4238277470
440000: 847346408
439000: 2474557496
438000: 2243092317
437000: 706909230
436000: 1303503693
435000: 1456129560
434000: 1073061079
433000: 692226634
432000: 186498656
431000: 2203415525
430000: 2183000701
429000: 1007776545
428000: 941117387
427000: 3805851413
426000: 1474193180
425000: 4231673903
424000: 2622576664
423000: 388097625
422000: 1165097488
421000: 3226044518
420000: 2531461570
419000: 1509806310
418000: 2667519114
417000: 1751592438
416000: 1286773513
415000: 1098182293
414000: 2111912709
413000: 1230737431
412000: 4090873946
411000: 3998652133
410000: 2486660396
409000: 2120483596
408000: 587404533
407000: 188697995
406000: 3265346093
405000: 4234961905
404000: 1211873901
403000: 4265173305
402000: 2208355316
401000: 3315952806
400000: 3917328941
399000: 2523594649
398000: 3805986783
397000: 2624925960
396000: 3716020189
395000: 2016201122
394000: 912930261
393000: 596904160
392000: 3571173642
391000: 2290782861
390000: 1162492227
389000: 1738718380
388000: 2599667355
387000: 2382332909
386000: 1471269037
385000: 2238392684
384000: 4034826126
383000: 1378654892
382000: 3702601850
381000: 397206179
380000: 2437704230
379000: 4187604139
378000: 779452169
377000: 2010372403
376000: 531902409
375000: 1371470602
374000: 4137796987
373000: 567426549
372000: 3082742955
371000: 2271575596
370000: 759731212
369000: 4063369437
368000: 299356452
367000: 536656228
366000: 3014961694
365000: 3016542135
364000: 2841873124
363000: 524434057
362000: 2887828889
361000: 3865529589
360000: 671363647
359000: 3104594256
358000: 1502485940
357000: 1776624159
356000: 4222478488
355000: 4127624139
354000: 2439477793
353000: 1593794891
352000: 591275342
351000: 2177291538
350000: 1923444781
349000: 758084193
348000: 775471359
347000: 191356974
346000: 494488375
345000: 1990489399
344000: 124118372
343000: 2046377904
342000: 1395427716
341000: 1342299790
340000: 38145994
339000: 2291884417
338000: 351940574
337000: 3984301480
336000: 2468666235
335000: 371500747
334000: 969922131
333000: 240854580
332000: 1644465214
331000: 1539846168
330000: 940087216
329000: 1491329232
328000: 2281687201
327000: 3030170550
326000: 3648503863
325000: 2037898355
324000: 174369956
323000: 2433605668
322000: 2334905107
321000: 1597704047
320000: 302297707
319000: 3209203690
318000: 3894539879
317000: 2868907580
316000: 2808087076
315000: 4034586233
314000: 3694191694
313000: 2001671958
312000: 559582279
311000: 3043016195
310000: 2785098502
309000: 4104602138
308000: 966154914
307000: 2446376687
306000: 789956605
305000: 1708137092
304000: 1733063901
303000: 2924555399
302000: 971356234
301000: 481382543
300000: 2647080988
299000: 4065744916
298000: 921140
297000: 654346784
296000: 485492098
295000: 217516816
294000: 4050820137
293000: 534726686
292000: 1686691079
291000: 1316587195
290000: 3746020838
289000: 1641967381
288000: 3492475215
287000: 3154885393
286000: 3686450617
285000: 3589739293
284000: 3558041700
283000: 4130142319
282000: 3132446063
281000: 982677436
280000: 799322395
279000: 151715214
278000: 3765942871
277000: 1712470933
276000: 3807622752
275000: 4163730108
274000: 1633425299
273000: 1654241631
272000: 1131025394
271000: 1375475855
270000: 553294237
269000: 4091487177
268000: 2841855980
267000: 2997369904
266000: 454385594
265000: 3757482634
264000: 3856197465
263000: 1084605457
262000: 2552759023
261000: 3786548799
260000: 272762545
259000: 2670277860
258000: 76233700
257000: 476168167
256000: 8969192
255000: 1998841030
254000: 1240074303
253000: 1771564446
252000: 710374418
251000: 821383716
250000: 3157726088
249000: 3083379502
248000: 2563632690
247000: 33723341
246000: 3303336748
245000: 4110677892
244000: 3811702913
243000: 53856215
242000: 243571468
241000: 52177779
240000: 46805590
239000: 1622010618
238000: 1321640849
237000: 3106837291
236000: 4102944642
235000: 137904396
234000: 339510135
233000: 88415957
232000: 3157666382
231000: 2571005912
230000: 3586247649
229000: 4172761781
228000: 2463305780
227000: 956927307
226000: 2169861547
225000: 1751989251
224000: 673059158
223000: 2782464516
222000: 3741392140
221000: 2856154963
220000: 3778376854
219000: 1538476717
218000: 2879698522
217000: 3734645735
216000: 1899042577
215000: 371356008
214000: 2416663698
213000: 1595919347
212000: 2816045438
211000: 132438808
210000: 1098603890
209000: 834913667
208000: 2707567283
207000: 3154122448
206000: 3696516104
205000: 1427952551
204000: 280496321
203000: 1185678745
202000: 3461951699
201000: 1369208434
200000: 3900136261
199000: 870818876
198000: 327248310
197000: 3116959470
196000: 1544241188
195000: 1568248814
194000: 2978831302
193000: 205660429
192000: 1704239501
191000: 3570135474
190000: 3878512103
189000: 1212729210
188000: 1873588815
187000: 324853813
186000: 432676298
185000: 1641364437
184000: 1568401301
183000: 525792402
182000: 861154382
181000: 2357325066
180000: 3626762590
179000: 4172125462
178000: 2108738993
177000: 2084782857
176000: 3956924509
175000: 17183073
174000: 3676839474
173000: 458250029
172000: 2635215219
171000: 1801029767
170000: 3602628987
169000: 370704281
168000: 177963345
167000: 924067814
166000: 3577678376
165000: 3717789117
164000: 3285809386
163000: 3738962897
162000: 3172510171
161000: 417992786
160000: 2591600214
159000: 3315096579
158000: 3590763949
157000: 198872871
156000: 2960653534
155000: 2246563682
154000: 2304045306
153000: 2647353543
152000: 2043381015
151000: 3952056867
150000: 2644058641
149000: 3477151018
148000: 1740210241
147000: 3314851112
146000: 1604832482
145000: 2572410736
144000: 1965059167
143000: 889666293
142000: 1024747903
141000: 226685285
140000: 3149168519
139000: 403638872
138000: 1725889104
137000: 1417402331
136000: 422304488
135000: 2595894054
134000: 4266597695
133000: 1116326556
132000: 3537080833
131000: 2181246909
130000: 1241997223
129000: 628191304
128000: 3074132403
127000: 2112958836
126000: 1371260930
125000: 2272975771
124000: 1379085607
123000: 1998991877
122000: 2760271255
121000: 3784187756
120000: 311188417
119000: 1123593459
118000: 1249155194
117000: 908703020
116000: 3765244393
115000: 3040869794
114000: 437536659
113000: 3343598822
112000: 2419089776
111000: 1263143640
110000: 1384687523
109000: 1727931349
108000: 2861733388
107000: 963829093
106000: 431354627
105000: 3568623360
104000: 2957399361
103000: 1071045618
102000: 3968457714
101000: 3448338394
100000: 2586060251
99000: 3401651822
98000: 1579089478
97000: 3722618916
96000: 759319595
95000: 1269278712
94000: 150489448
93000: 390013662
92000: 3663029784
91000: 555197170
90000: 166476858
89000: 1658807720
88000: 3430520531
87000: 2946861093
86000: 3000600326
85000: 300034452
84000: 2813719249
83000: 3009927425
82000: 1127728469
81000: 2667791855
80000: 2632316050
79000: 2180301200
78000: 418999983
77000: 4254858933
76000: 2728734498
75000: 1863202698
74000: 4226419921
73000: 1917572494
72000: 3117082625
71000: 1032601538
70000: 2992135524
69000: 670119660
68000: 638731522
67000: 1460114012
66000: 1232274665
65000: 3667669961
64000: 191277965
63000: 3868442802
62000: 700664540
61000: 2271087482
60000: 3274078227
59000: 159900296
58000: 2778747772
57000: 2788477153
56000: 3965957780
55000: 2276993918
54000: 1986966104
53000: 3416414682
52000: 2162594060
51000: 2947744069
50000: 4024793290
49000: 631161701
48000: 728285173
47000: 1487641693
46000: 4049519424
45000: 613160608
44000: 1566126172
43000: 3731725133
42000: 2746368727
41000: 4168967735
40000: 1319649932
39000: 2964978784
38000: 967937134
37000: 3116555742
36000: 2279790642
35000: 2852914953
34000: 1040410911
33000: 226200467
32000: 1765748697
31000: 1418838964
30000: 1362983292
29000: 2877029789
28000: 583076938
27000: 2797138728
26000: 3033567067
25000: 3902265889
24000: 3287868661
23000: 2411740885
22000: 2747756860
21000: 1889759908
20000: 2975722149
19000: 3027693370
18000: 2418258302
17000: 490864179
16000: 1944489573
15000: 4212838860
14000: 1782397962
13000: 1981080238
12000: 1213651424
11000: 1407527546
10000: 661520991
9000: 143129551
8000: 3293448370
7000: 764314400
6000: 2246553770
5000: 2459308892
4000: 3776833152
3000: 2208260083
2000: 2845746745
1000: 2068042552
0: 290958364
Exiting @ tick 521167228000 because target called exit()

829
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,829 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.521167 # Number of seconds simulated
sim_ticks 521167228000 # Number of ticks simulated
final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 492017 # Simulator instruction rate (inst/s)
host_op_rate 492017 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 276083455 # Simulator tick rate (ticks/s)
host_mem_usage 263220 # Number of bytes of host memory used
host_seconds 1887.72 # Real time elapsed on the host
sim_insts 928789150 # Number of instructions simulated
sim_ops 928789150 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 185984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory
system.physmem.bytes_read::total 18706880 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 185984 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 185984 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2906 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory
system.physmem.num_reads::total 292295 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 356861 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 35537338 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 35894199 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 356861 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 356861 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8188757 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8188757 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8188757 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 356861 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 35537338 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 44082956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 292295 # Number of read requests accepted
system.physmem.writeReqs 66683 # Number of write requests accepted
system.physmem.readBursts 292295 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 18686976 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue
system.physmem.bytesWritten 4265856 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18706880 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 18028 # Per bank write bursts
system.physmem.perBankRdBursts::1 18369 # Per bank write bursts
system.physmem.perBankRdBursts::2 18396 # Per bank write bursts
system.physmem.perBankRdBursts::3 18341 # Per bank write bursts
system.physmem.perBankRdBursts::4 18255 # Per bank write bursts
system.physmem.perBankRdBursts::5 18258 # Per bank write bursts
system.physmem.perBankRdBursts::6 18325 # Per bank write bursts
system.physmem.perBankRdBursts::7 18297 # Per bank write bursts
system.physmem.perBankRdBursts::8 18227 # Per bank write bursts
system.physmem.perBankRdBursts::9 18235 # Per bank write bursts
system.physmem.perBankRdBursts::10 18232 # Per bank write bursts
system.physmem.perBankRdBursts::11 18375 # Per bank write bursts
system.physmem.perBankRdBursts::12 18268 # Per bank write bursts
system.physmem.perBankRdBursts::13 18134 # Per bank write bursts
system.physmem.perBankRdBursts::14 18057 # Per bank write bursts
system.physmem.perBankRdBursts::15 18187 # Per bank write bursts
system.physmem.perBankWrBursts::0 4123 # Per bank write bursts
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
system.physmem.perBankWrBursts::2 4221 # Per bank write bursts
system.physmem.perBankWrBursts::3 4157 # Per bank write bursts
system.physmem.perBankWrBursts::4 4141 # Per bank write bursts
system.physmem.perBankWrBursts::5 4097 # Per bank write bursts
system.physmem.perBankWrBursts::6 4260 # Per bank write bursts
system.physmem.perBankWrBursts::7 4224 # Per bank write bursts
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
system.physmem.perBankWrBursts::9 4192 # Per bank write bursts
system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 521167139500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 292295 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 291434 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 895 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 896 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4059 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 95989 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 239.106731 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 159.105135 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 271.560992 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 28950 30.16% 30.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 41784 43.53% 73.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11694 12.18% 85.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2599 2.71% 88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 913 0.95% 89.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 756 0.79% 90.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 331 0.34% 90.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 447 0.47% 91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8515 8.87% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 95989 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 68.753823 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 34.637200 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 730.740597 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.441539 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.421503 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.829633 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3159 77.92% 77.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 895 22.08% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads
system.physmem.totQLat 15194551500 # Total ticks spent queuing
system.physmem.totMemAccLat 20669251500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1459920000 # Total ticks spent in databus transfers
system.physmem.avgQLat 52038.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 70788.99 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 35.86 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 8.19 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 35.89 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 8.19 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.34 # Data bus utilization in percentage
system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing
system.physmem.readRowHits 210474 # Number of row buffer hits during reads
system.physmem.writeRowHits 52167 # Number of row buffer hits during writes
system.physmem.readRowHitRate 72.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes
system.physmem.avgGap 1451808.02 # Average gap between requests
system.physmem.pageHitRate 73.23 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 341770380 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 181632495 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1044360660 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 174280140 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 28691395200.000008 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 8105258640 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1605839040 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 57337999170 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 51043667520 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 64046185080 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 212592411075 # Total energy per rank (pJ)
system.physmem_0.averagePower 407.915916 # Core power per rank (mW)
system.physmem_0.totalIdleTime 499165974500 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 3167480750 # Time in different power states
system.physmem_0.memoryStateTime::REF 12206580000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 240498579500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 132926079750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 6626927000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 125741581000 # Time in different power states
system.physmem_1.actEnergy 343648200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 182645760 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1040405100 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 173653740 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 28803874320.000008 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 8196268830 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1616284320 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 57528037740 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 51141308640 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 63870409695 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 212914803135 # Total energy per rank (pJ)
system.physmem_1.averagePower 408.534516 # Core power per rank (mW)
system.physmem_1.totalIdleTime 498942805750 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 3183963500 # Time in different power states
system.physmem_1.memoryStateTime::REF 12254448000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 239604631750 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 133180372750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 6785962500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 126157849500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 123851675 # Number of BP lookups
system.cpu.branchPred.condPredicted 79872959 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 686742 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 102066154 # Number of BTB lookups
system.cpu.branchPred.BTBHits 68190152 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 66.809759 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 18697401 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 11223 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 14052181 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 14048615 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 3566 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 11656 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 237539296 # DTB read hits
system.cpu.dtb.read_misses 195211 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 237734507 # DTB read accesses
system.cpu.dtb.write_hits 98305023 # DTB write hits
system.cpu.dtb.write_misses 7170 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 98312193 # DTB write accesses
system.cpu.dtb.data_hits 335844319 # DTB hits
system.cpu.dtb.data_misses 202381 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 336046700 # DTB accesses
system.cpu.itb.fetch_hits 286584578 # ITB hits
system.cpu.itb.fetch_misses 119 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 286584697 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1042334456 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928789150 # Number of instructions committed
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
system.cpu.discardedOps 319598 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.122251 # CPI: cycles per instruction
system.cpu.ipc 0.891066 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction
system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction
system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::MemRead 228135214 24.56% 88.39% # Class of committed instruction
system.cpu.op_class_0::MemWrite 94471145 10.17% 98.56% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 9570033 1.03% 99.59% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 3836926 0.41% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 928789150 # Class of committed instruction
system.cpu.tickCycles 962817000 # Number of cycles that the object actually ticked
system.cpu.idleCycles 79517456 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 776559 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.209717 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 320318705 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 410.320442 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 968708500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.209717 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999075 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999075 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 957 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1349 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 643115675 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 643115675 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 222154657 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 222154657 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98164048 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 98164048 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 320318705 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 320318705 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 320318705 # number of overall hits
system.cpu.dcache.overall_hits::total 320318705 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 137152 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 137152 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 848805 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 848805 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 848805 # number of overall misses
system.cpu.dcache.overall_misses::total 848805 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 36922839000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 36922839000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10957317000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10957317000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 47880156000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 47880156000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 47880156000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 47880156000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 222866310 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 222866310 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 321167510 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 321167510 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 321167510 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 321167510 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51883.205720 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51883.205720 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79891.777007 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 79891.777007 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56408.899571 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56408.899571 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks
system.cpu.dcache.writebacks::total 88440 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68141 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 68141 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 68150 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 68150 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 68150 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 68150 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711644 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711644 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 780655 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36210490500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36210490500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5501688000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5501688000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41712178500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 41712178500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41712178500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 41712178500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50882.871913 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50882.871913 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79721.899407 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79721.899407 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 10581 # number of replacements
system.cpu.icache.tags.tagsinuse 1690.101724 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 286572250 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 12327 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 23247.525756 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1690.101724 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.825245 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.825245 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 573181483 # Number of tag accesses
system.cpu.icache.tags.data_accesses 573181483 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 286572250 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 286572250 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 286572250 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 286572250 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 286572250 # number of overall hits
system.cpu.icache.overall_hits::total 286572250 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 12328 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 12328 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 12328 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 12328 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 12328 # number of overall misses
system.cpu.icache.overall_misses::total 12328 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 376885500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 376885500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 376885500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 376885500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 376885500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 376885500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 286584578 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 286584578 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 286584578 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 286584578 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 286584578 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 286584578 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30571.503894 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 30571.503894 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 30571.503894 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 30571.503894 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 10581 # number of writebacks
system.cpu.icache.writebacks::total 10581 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 12328 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 12328 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 12328 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 364558500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 364558500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 364558500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 364558500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 364558500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 364558500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29571.585010 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29571.585010 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 259984 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32658.667775 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1287369 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 292752 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.397473 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 3857784000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 51.730334 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.865838 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 32527.071603 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.001579 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002437 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.992647 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996663 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2875 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12933736 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12933736 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88440 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88440 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10581 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 10581 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9421 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 9421 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488900 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 488900 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 9421 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 491266 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 500687 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 9421 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 491266 # number of overall hits
system.cpu.l2cache.overall_hits::total 500687 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2907 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2907 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222744 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 222744 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2907 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 289389 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 292296 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2907 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 289389 # number of overall misses
system.cpu.l2cache.overall_misses::total 292296 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5373301500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5373301500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 247147500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 247147500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30009565500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 30009565500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 247147500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 35382867000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 35630014500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 247147500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 35382867000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 35630014500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88440 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88440 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 10581 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 10581 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12328 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 12328 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711644 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 711644 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 12328 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 780655 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 792983 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 12328 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 792983 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235805 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235805 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312999 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312999 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235805 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.368603 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235805 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.368603 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80625.725861 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80625.725861 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85018.059856 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85018.059856 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134726.706443 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134726.706443 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 121897.030750 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 121897.030750 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2907 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2907 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2907 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 292296 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2907 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 292296 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4706851500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4706851500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 218087500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 218087500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27782125500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27782125500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218087500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32488977000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 32707064500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218087500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32488977000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 32707064500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235805 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.368603 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.368603 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70625.725861 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70625.725861 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.499828 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.499828 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124726.706443 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124726.706443 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1580123 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 787140 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 723971 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10581 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 881420 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 12328 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35236 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2373105 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1466112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 57088192 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 259984 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1052967 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001991 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.044571 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1050871 99.80% 99.80% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2096 0.20% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1052967 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 889082500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 18490500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1170982500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 550183 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 257888 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 225650 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
system.membus.trans_dist::CleanEvict 191205 # Transaction distribution
system.membus.trans_dist::ReadExReq 66645 # Transaction distribution
system.membus.trans_dist::ReadExResp 66645 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 225650 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 842478 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974592 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22974592 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 292295 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 292295 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 292295 # Request fanout histogram
system.membus.reqLayer0.occupancy 925387500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 1555624500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

825
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,825 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

8
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,8 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)
warn: ignoring syscall sigprocmask(1, ...)

653
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -1,653 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:46
gem5 executing on e108600-lin, pid 28086
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
634000: 545393176
633000: 3107247613
632000: 897887463
631000: 806367477
630000: 1682157095
629000: 1188376072
628000: 4076707785
627000: 3521684454
626000: 3144526095
625000: 1399223384
624000: 3380494826
623000: 4086509498
622000: 1473819475
621000: 638751284
620000: 3149483163
619000: 1489851375
618000: 1447059134
617000: 136329498
616000: 1288452788
615000: 3949816816
614000: 318984246
613000: 1019963195
612000: 2875280299
611000: 2997394777
610000: 4014932807
609000: 2291235006
608000: 355450951
607000: 201970399
606000: 3626124461
605000: 2207253273
604000: 2243886712
603000: 46791684
602000: 3176322294
601000: 1120582847
600000: 411705454
599000: 3162380308
598000: 2732375303
597000: 1376844609
596000: 3003023122
595000: 3869968535
594000: 1327286554
593000: 160655029
592000: 2038558826
591000: 3948772976
590000: 439262378
589000: 329537197
588000: 3678661972
587000: 4240182727
586000: 2283602206
585000: 1129811410
584000: 2831949168
583000: 1224559023
582000: 3161562107
581000: 2695467835
580000: 1234192577
579000: 1974816198
578000: 449576701
577000: 1424873035
576000: 2370444290
575000: 1743089134
574000: 2624046998
573000: 2071148441
572000: 2449219691
571000: 3774476172
570000: 1111630327
569000: 121721805
568000: 2981212266
567000: 3811833647
566000: 3676851843
565000: 1766252334
564000: 1622887950
563000: 1684409857
562000: 1686489387
561000: 610219569
560000: 2705092362
559000: 108031723
558000: 1316736987
557000: 2434129258
556000: 1411819652
555000: 1173886179
554000: 3044539233
553000: 151590417
552000: 3759426289
551000: 3451520306
550000: 294242855
549000: 890241051
548000: 876385779
547000: 119864600
546000: 3065674956
545000: 1670853168
544000: 997261561
543000: 660227344
542000: 3132294889
541000: 521956271
540000: 1133928405
539000: 3838154786
538000: 58624572
537000: 3544030439
536000: 432804999
535000: 1021857051
534000: 2644812356
533000: 773094580
532000: 901027171
531000: 3976696839
530000: 4167278216
529000: 504481120
528000: 320399857
527000: 638048690
526000: 3348998474
525000: 2660662065
524000: 2641437803
523000: 626927006
522000: 4063917554
521000: 3212249308
520000: 2561025301
519000: 1078140141
518000: 653939181
517000: 2154098204
516000: 3773089676
515000: 2568381435
514000: 3838886937
513000: 941125346
512000: 1318900410
511000: 297013287
510000: 241723934
509000: 1835499795
508000: 2309451230
507000: 1174814430
506000: 3615943386
505000: 51034971
504000: 3950453295
503000: 4186097241
502000: 327518343
501000: 3052462710
500000: 1586937404
499000: 2169094819
498000: 3613195151
497000: 817359591
496000: 1470916579
495000: 2091261583
494000: 2080080890
493000: 1772858697
492000: 2085609872
491000: 3280632925
490000: 1689322569
489000: 2947406469
488000: 765163324
487000: 3122594732
486000: 3385418480
485000: 1712345567
484000: 3675825158
483000: 1558929764
482000: 2672493410
481000: 3822528440
480000: 3741769935
479000: 2794026235
478000: 2541364185
477000: 3964482316
476000: 1202478165
475000: 4027617791
474000: 1905026738
473000: 2573787636
472000: 1170529797
471000: 2272525618
470000: 820833429
469000: 3219769529
468000: 2121197441
467000: 269331764
466000: 3038487237
465000: 2462675338
464000: 2703163101
463000: 547052037
462000: 3454526671
461000: 2124641794
460000: 1043737466
459000: 1785834964
458000: 3312335313
457000: 1213835042
456000: 3099430685
455000: 3003350806
454000: 3646781335
453000: 1474165966
452000: 705795987
451000: 2723908407
450000: 1323056304
449000: 1157256530
448000: 4077983523
447000: 3189085703
446000: 2241002747
445000: 3229050072
444000: 3500150226
443000: 1290722604
442000: 1866107725
441000: 4238277470
440000: 847346408
439000: 2474557496
438000: 2243092317
437000: 706909230
436000: 1303503693
435000: 1456129560
434000: 1073061079
433000: 692226634
432000: 186498656
431000: 2203415525
430000: 2183000701
429000: 1007776545
428000: 941117387
427000: 3805851413
426000: 1474193180
425000: 4231673903
424000: 2622576664
423000: 388097625
422000: 1165097488
421000: 3226044518
420000: 2531461570
419000: 1509806310
418000: 2667519114
417000: 1751592438
416000: 1286773513
415000: 1098182293
414000: 2111912709
413000: 1230737431
412000: 4090873946
411000: 3998652133
410000: 2486660396
409000: 2120483596
408000: 587404533
407000: 188697995
406000: 3265346093
405000: 4234961905
404000: 1211873901
403000: 4265173305
402000: 2208355316
401000: 3315952806
400000: 3917328941
399000: 2523594649
398000: 3805986783
397000: 2624925960
396000: 3716020189
395000: 2016201122
394000: 912930261
393000: 596904160
392000: 3571173642
391000: 2290782861
390000: 1162492227
389000: 1738718380
388000: 2599667355
387000: 2382332909
386000: 1471269037
385000: 2238392684
384000: 4034826126
383000: 1378654892
382000: 3702601850
381000: 397206179
380000: 2437704230
379000: 4187604139
378000: 779452169
377000: 2010372403
376000: 531902409
375000: 1371470602
374000: 4137796987
373000: 567426549
372000: 3082742955
371000: 2271575596
370000: 759731212
369000: 4063369437
368000: 299356452
367000: 536656228
366000: 3014961694
365000: 3016542135
364000: 2841873124
363000: 524434057
362000: 2887828889
361000: 3865529589
360000: 671363647
359000: 3104594256
358000: 1502485940
357000: 1776624159
356000: 4222478488
355000: 4127624139
354000: 2439477793
353000: 1593794891
352000: 591275342
351000: 2177291538
350000: 1923444781
349000: 758084193
348000: 775471359
347000: 191356974
346000: 494488375
345000: 1990489399
344000: 124118372
343000: 2046377904
342000: 1395427716
341000: 1342299790
340000: 38145994
339000: 2291884417
338000: 351940574
337000: 3984301480
336000: 2468666235
335000: 371500747
334000: 969922131
333000: 240854580
332000: 1644465214
331000: 1539846168
330000: 940087216
329000: 1491329232
328000: 2281687201
327000: 3030170550
326000: 3648503863
325000: 2037898355
324000: 174369956
323000: 2433605668
322000: 2334905107
321000: 1597704047
320000: 302297707
319000: 3209203690
318000: 3894539879
317000: 2868907580
316000: 2808087076
315000: 4034586233
314000: 3694191694
313000: 2001671958
312000: 559582279
311000: 3043016195
310000: 2785098502
309000: 4104602138
308000: 966154914
307000: 2446376687
306000: 789956605
305000: 1708137092
304000: 1733063901
303000: 2924555399
302000: 971356234
301000: 481382543
300000: 2647080988
299000: 4065744916
298000: 921140
297000: 654346784
296000: 485492098
295000: 217516816
294000: 4050820137
293000: 534726686
292000: 1686691079
291000: 1316587195
290000: 3746020838
289000: 1641967381
288000: 3492475215
287000: 3154885393
286000: 3686450617
285000: 3589739293
284000: 3558041700
283000: 4130142319
282000: 3132446063
281000: 982677436
280000: 799322395
279000: 151715214
278000: 3765942871
277000: 1712470933
276000: 3807622752
275000: 4163730108
274000: 1633425299
273000: 1654241631
272000: 1131025394
271000: 1375475855
270000: 553294237
269000: 4091487177
268000: 2841855980
267000: 2997369904
266000: 454385594
265000: 3757482634
264000: 3856197465
263000: 1084605457
262000: 2552759023
261000: 3786548799
260000: 272762545
259000: 2670277860
258000: 76233700
257000: 476168167
256000: 8969192
255000: 1998841030
254000: 1240074303
253000: 1771564446
252000: 710374418
251000: 821383716
250000: 3157726088
249000: 3083379502
248000: 2563632690
247000: 33723341
246000: 3303336748
245000: 4110677892
244000: 3811702913
243000: 53856215
242000: 243571468
241000: 52177779
240000: 46805590
239000: 1622010618
238000: 1321640849
237000: 3106837291
236000: 4102944642
235000: 137904396
234000: 339510135
233000: 88415957
232000: 3157666382
231000: 2571005912
230000: 3586247649
229000: 4172761781
228000: 2463305780
227000: 956927307
226000: 2169861547
225000: 1751989251
224000: 673059158
223000: 2782464516
222000: 3741392140
221000: 2856154963
220000: 3778376854
219000: 1538476717
218000: 2879698522
217000: 3734645735
216000: 1899042577
215000: 371356008
214000: 2416663698
213000: 1595919347
212000: 2816045438
211000: 132438808
210000: 1098603890
209000: 834913667
208000: 2707567283
207000: 3154122448
206000: 3696516104
205000: 1427952551
204000: 280496321
203000: 1185678745
202000: 3461951699
201000: 1369208434
200000: 3900136261
199000: 870818876
198000: 327248310
197000: 3116959470
196000: 1544241188
195000: 1568248814
194000: 2978831302
193000: 205660429
192000: 1704239501
191000: 3570135474
190000: 3878512103
189000: 1212729210
188000: 1873588815
187000: 324853813
186000: 432676298
185000: 1641364437
184000: 1568401301
183000: 525792402
182000: 861154382
181000: 2357325066
180000: 3626762590
179000: 4172125462
178000: 2108738993
177000: 2084782857
176000: 3956924509
175000: 17183073
174000: 3676839474
173000: 458250029
172000: 2635215219
171000: 1801029767
170000: 3602628987
169000: 370704281
168000: 177963345
167000: 924067814
166000: 3577678376
165000: 3717789117
164000: 3285809386
163000: 3738962897
162000: 3172510171
161000: 417992786
160000: 2591600214
159000: 3315096579
158000: 3590763949
157000: 198872871
156000: 2960653534
155000: 2246563682
154000: 2304045306
153000: 2647353543
152000: 2043381015
151000: 3952056867
150000: 2644058641
149000: 3477151018
148000: 1740210241
147000: 3314851112
146000: 1604832482
145000: 2572410736
144000: 1965059167
143000: 889666293
142000: 1024747903
141000: 226685285
140000: 3149168519
139000: 403638872
138000: 1725889104
137000: 1417402331
136000: 422304488
135000: 2595894054
134000: 4266597695
133000: 1116326556
132000: 3537080833
131000: 2181246909
130000: 1241997223
129000: 628191304
128000: 3074132403
127000: 2112958836
126000: 1371260930
125000: 2272975771
124000: 1379085607
123000: 1998991877
122000: 2760271255
121000: 3784187756
120000: 311188417
119000: 1123593459
118000: 1249155194
117000: 908703020
116000: 3765244393
115000: 3040869794
114000: 437536659
113000: 3343598822
112000: 2419089776
111000: 1263143640
110000: 1384687523
109000: 1727931349
108000: 2861733388
107000: 963829093
106000: 431354627
105000: 3568623360
104000: 2957399361
103000: 1071045618
102000: 3968457714
101000: 3448338394
100000: 2586060251
99000: 3401651822
98000: 1579089478
97000: 3722618916
96000: 759319595
95000: 1269278712
94000: 150489448
93000: 390013662
92000: 3663029784
91000: 555197170
90000: 166476858
89000: 1658807720
88000: 3430520531
87000: 2946861093
86000: 3000600326
85000: 300034452
84000: 2813719249
83000: 3009927425
82000: 1127728469
81000: 2667791855
80000: 2632316050
79000: 2180301200
78000: 418999983
77000: 4254858933
76000: 2728734498
75000: 1863202698
74000: 4226419921
73000: 1917572494
72000: 3117082625
71000: 1032601538
70000: 2992135524
69000: 670119660
68000: 638731522
67000: 1460114012
66000: 1232274665
65000: 3667669961
64000: 191277965
63000: 3868442802
62000: 700664540
61000: 2271087482
60000: 3274078227
59000: 159900296
58000: 2778747772
57000: 2788477153
56000: 3965957780
55000: 2276993918
54000: 1986966104
53000: 3416414682
52000: 2162594060
51000: 2947744069
50000: 4024793290
49000: 631161701
48000: 728285173
47000: 1487641693
46000: 4049519424
45000: 613160608
44000: 1566126172
43000: 3731725133
42000: 2746368727
41000: 4168967735
40000: 1319649932
39000: 2964978784
38000: 967937134
37000: 3116555742
36000: 2279790642
35000: 2852914953
34000: 1040410911
33000: 226200467
32000: 1765748697
31000: 1418838964
30000: 1362983292
29000: 2877029789
28000: 583076938
27000: 2797138728
26000: 3033567067
25000: 3902265889
24000: 3287868661
23000: 2411740885
22000: 2747756860
21000: 1889759908
20000: 2975722149
19000: 3027693370
18000: 2418258302
17000: 490864179
16000: 1944489573
15000: 4212838860
14000: 1782397962
13000: 1981080238
12000: 1213651424
11000: 1407527546
10000: 661520991
9000: 143129551
8000: 3293448370
7000: 764314400
6000: 2246553770
5000: 2459308892
4000: 3776833152
3000: 2208260083
2000: 2845746745
1000: 2068042552
0: 290958364
Exiting @ tick 180964610500 because target called exit()

1097
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

203
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -1,203 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,7 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)
warn: ignoring syscall sigprocmask(1, ...)

653
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,653 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51
gem5 started Jul 21 2016 14:09:28
gem5 executing on e108600-lin, pid 4304
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
634000: 545393176
633000: 3107247613
632000: 897887463
631000: 806367477
630000: 1682157095
629000: 1188376072
628000: 4076707785
627000: 3521684454
626000: 3144526095
625000: 1399223384
624000: 3380494826
623000: 4086509498
622000: 1473819475
621000: 638751284
620000: 3149483163
619000: 1489851375
618000: 1447059134
617000: 136329498
616000: 1288452788
615000: 3949816816
614000: 318984246
613000: 1019963195
612000: 2875280299
611000: 2997394777
610000: 4014932807
609000: 2291235006
608000: 355450951
607000: 201970399
606000: 3626124461
605000: 2207253273
604000: 2243886712
603000: 46791684
602000: 3176322294
601000: 1120582847
600000: 411705454
599000: 3162380308
598000: 2732375303
597000: 1376844609
596000: 3003023122
595000: 3869968535
594000: 1327286554
593000: 160655029
592000: 2038558826
591000: 3948772976
590000: 439262378
589000: 329537197
588000: 3678661972
587000: 4240182727
586000: 2283602206
585000: 1129811410
584000: 2831949168
583000: 1224559023
582000: 3161562107
581000: 2695467835
580000: 1234192577
579000: 1974816198
578000: 449576701
577000: 1424873035
576000: 2370444290
575000: 1743089134
574000: 2624046998
573000: 2071148441
572000: 2449219691
571000: 3774476172
570000: 1111630327
569000: 121721805
568000: 2981212266
567000: 3811833647
566000: 3676851843
565000: 1766252334
564000: 1622887950
563000: 1684409857
562000: 1686489387
561000: 610219569
560000: 2705092362
559000: 108031723
558000: 1316736987
557000: 2434129258
556000: 1411819652
555000: 1173886179
554000: 3044539233
553000: 151590417
552000: 3759426289
551000: 3451520306
550000: 294242855
549000: 890241051
548000: 876385779
547000: 119864600
546000: 3065674956
545000: 1670853168
544000: 997261561
543000: 660227344
542000: 3132294889
541000: 521956271
540000: 1133928405
539000: 3838154786
538000: 58624572
537000: 3544030439
536000: 432804999
535000: 1021857051
534000: 2644812356
533000: 773094580
532000: 901027171
531000: 3976696839
530000: 4167278216
529000: 504481120
528000: 320399857
527000: 638048690
526000: 3348998474
525000: 2660662065
524000: 2641437803
523000: 626927006
522000: 4063917554
521000: 3212249308
520000: 2561025301
519000: 1078140141
518000: 653939181
517000: 2154098204
516000: 3773089676
515000: 2568381435
514000: 3838886937
513000: 941125346
512000: 1318900410
511000: 297013287
510000: 241723934
509000: 1835499795
508000: 2309451230
507000: 1174814430
506000: 3615943386
505000: 51034971
504000: 3950453295
503000: 4186097241
502000: 327518343
501000: 3052462710
500000: 1586937404
499000: 2169094819
498000: 3613195151
497000: 817359591
496000: 1470916579
495000: 2091261583
494000: 2080080890
493000: 1772858697
492000: 2085609872
491000: 3280632925
490000: 1689322569
489000: 2947406469
488000: 765163324
487000: 3122594732
486000: 3385418480
485000: 1712345567
484000: 3675825158
483000: 1558929764
482000: 2672493410
481000: 3822528440
480000: 3741769935
479000: 2794026235
478000: 2541364185
477000: 3964482316
476000: 1202478165
475000: 4027617791
474000: 1905026738
473000: 2573787636
472000: 1170529797
471000: 2272525618
470000: 820833429
469000: 3219769529
468000: 2121197441
467000: 269331764
466000: 3038487237
465000: 2462675338
464000: 2703163101
463000: 547052037
462000: 3454526671
461000: 2124641794
460000: 1043737466
459000: 1785834964
458000: 3312335313
457000: 1213835042
456000: 3099430685
455000: 3003350806
454000: 3646781335
453000: 1474165966
452000: 705795987
451000: 2723908407
450000: 1323056304
449000: 1157256530
448000: 4077983523
447000: 3189085703
446000: 2241002747
445000: 3229050072
444000: 3500150226
443000: 1290722604
442000: 1866107725
441000: 4238277470
440000: 847346408
439000: 2474557496
438000: 2243092317
437000: 706909230
436000: 1303503693
435000: 1456129560
434000: 1073061079
433000: 692226634
432000: 186498656
431000: 2203415525
430000: 2183000701
429000: 1007776545
428000: 941117387
427000: 3805851413
426000: 1474193180
425000: 4231673903
424000: 2622576664
423000: 388097625
422000: 1165097488
421000: 3226044518
420000: 2531461570
419000: 1509806310
418000: 2667519114
417000: 1751592438
416000: 1286773513
415000: 1098182293
414000: 2111912709
413000: 1230737431
412000: 4090873946
411000: 3998652133
410000: 2486660396
409000: 2120483596
408000: 587404533
407000: 188697995
406000: 3265346093
405000: 4234961905
404000: 1211873901
403000: 4265173305
402000: 2208355316
401000: 3315952806
400000: 3917328941
399000: 2523594649
398000: 3805986783
397000: 2624925960
396000: 3716020189
395000: 2016201122
394000: 912930261
393000: 596904160
392000: 3571173642
391000: 2290782861
390000: 1162492227
389000: 1738718380
388000: 2599667355
387000: 2382332909
386000: 1471269037
385000: 2238392684
384000: 4034826126
383000: 1378654892
382000: 3702601850
381000: 397206179
380000: 2437704230
379000: 4187604139
378000: 779452169
377000: 2010372403
376000: 531902409
375000: 1371470602
374000: 4137796987
373000: 567426549
372000: 3082742955
371000: 2271575596
370000: 759731212
369000: 4063369437
368000: 299356452
367000: 536656228
366000: 3014961694
365000: 3016542135
364000: 2841873124
363000: 524434057
362000: 2887828889
361000: 3865529589
360000: 671363647
359000: 3104594256
358000: 1502485940
357000: 1776624159
356000: 4222478488
355000: 4127624139
354000: 2439477793
353000: 1593794891
352000: 591275342
351000: 2177291538
350000: 1923444781
349000: 758084193
348000: 775471359
347000: 191356974
346000: 494488375
345000: 1990489399
344000: 124118372
343000: 2046377904
342000: 1395427716
341000: 1342299790
340000: 38145994
339000: 2291884417
338000: 351940574
337000: 3984301480
336000: 2468666235
335000: 371500747
334000: 969922131
333000: 240854580
332000: 1644465214
331000: 1539846168
330000: 940087216
329000: 1491329232
328000: 2281687201
327000: 3030170550
326000: 3648503863
325000: 2037898355
324000: 174369956
323000: 2433605668
322000: 2334905107
321000: 1597704047
320000: 302297707
319000: 3209203690
318000: 3894539879
317000: 2868907580
316000: 2808087076
315000: 4034586233
314000: 3694191694
313000: 2001671958
312000: 559582279
311000: 3043016195
310000: 2785098502
309000: 4104602138
308000: 966154914
307000: 2446376687
306000: 789956605
305000: 1708137092
304000: 1733063901
303000: 2924555399
302000: 971356234
301000: 481382543
300000: 2647080988
299000: 4065744916
298000: 921140
297000: 654346784
296000: 485492098
295000: 217516816
294000: 4050820137
293000: 534726686
292000: 1686691079
291000: 1316587195
290000: 3746020838
289000: 1641967381
288000: 3492475215
287000: 3154885393
286000: 3686450617
285000: 3589739293
284000: 3558041700
283000: 4130142319
282000: 3132446063
281000: 982677436
280000: 799322395
279000: 151715214
278000: 3765942871
277000: 1712470933
276000: 3807622752
275000: 4163730108
274000: 1633425299
273000: 1654241631
272000: 1131025394
271000: 1375475855
270000: 553294237
269000: 4091487177
268000: 2841855980
267000: 2997369904
266000: 454385594
265000: 3757482634
264000: 3856197465
263000: 1084605457
262000: 2552759023
261000: 3786548799
260000: 272762545
259000: 2670277860
258000: 76233700
257000: 476168167
256000: 8969192
255000: 1998841030
254000: 1240074303
253000: 1771564446
252000: 710374418
251000: 821383716
250000: 3157726088
249000: 3083379502
248000: 2563632690
247000: 33723341
246000: 3303336748
245000: 4110677892
244000: 3811702913
243000: 53856215
242000: 243571468
241000: 52177779
240000: 46805590
239000: 1622010618
238000: 1321640849
237000: 3106837291
236000: 4102944642
235000: 137904396
234000: 339510135
233000: 88415957
232000: 3157666382
231000: 2571005912
230000: 3586247649
229000: 4172761781
228000: 2463305780
227000: 956927307
226000: 2169861547
225000: 1751989251
224000: 673059158
223000: 2782464516
222000: 3741392140
221000: 2856154963
220000: 3778376854
219000: 1538476717
218000: 2879698522
217000: 3734645735
216000: 1899042577
215000: 371356008
214000: 2416663698
213000: 1595919347
212000: 2816045438
211000: 132438808
210000: 1098603890
209000: 834913667
208000: 2707567283
207000: 3154122448
206000: 3696516104
205000: 1427952551
204000: 280496321
203000: 1185678745
202000: 3461951699
201000: 1369208434
200000: 3900136261
199000: 870818876
198000: 327248310
197000: 3116959470
196000: 1544241188
195000: 1568248814
194000: 2978831302
193000: 205660429
192000: 1704239501
191000: 3570135474
190000: 3878512103
189000: 1212729210
188000: 1873588815
187000: 324853813
186000: 432676298
185000: 1641364437
184000: 1568401301
183000: 525792402
182000: 861154382
181000: 2357325066
180000: 3626762590
179000: 4172125462
178000: 2108738993
177000: 2084782857
176000: 3956924509
175000: 17183073
174000: 3676839474
173000: 458250029
172000: 2635215219
171000: 1801029767
170000: 3602628987
169000: 370704281
168000: 177963345
167000: 924067814
166000: 3577678376
165000: 3717789117
164000: 3285809386
163000: 3738962897
162000: 3172510171
161000: 417992786
160000: 2591600214
159000: 3315096579
158000: 3590763949
157000: 198872871
156000: 2960653534
155000: 2246563682
154000: 2304045306
153000: 2647353543
152000: 2043381015
151000: 3952056867
150000: 2644058641
149000: 3477151018
148000: 1740210241
147000: 3314851112
146000: 1604832482
145000: 2572410736
144000: 1965059167
143000: 889666293
142000: 1024747903
141000: 226685285
140000: 3149168519
139000: 403638872
138000: 1725889104
137000: 1417402331
136000: 422304488
135000: 2595894054
134000: 4266597695
133000: 1116326556
132000: 3537080833
131000: 2181246909
130000: 1241997223
129000: 628191304
128000: 3074132403
127000: 2112958836
126000: 1371260930
125000: 2272975771
124000: 1379085607
123000: 1998991877
122000: 2760271255
121000: 3784187756
120000: 311188417
119000: 1123593459
118000: 1249155194
117000: 908703020
116000: 3765244393
115000: 3040869794
114000: 437536659
113000: 3343598822
112000: 2419089776
111000: 1263143640
110000: 1384687523
109000: 1727931349
108000: 2861733388
107000: 963829093
106000: 431354627
105000: 3568623360
104000: 2957399361
103000: 1071045618
102000: 3968457714
101000: 3448338394
100000: 2586060251
99000: 3401651822
98000: 1579089478
97000: 3722618916
96000: 759319595
95000: 1269278712
94000: 150489448
93000: 390013662
92000: 3663029784
91000: 555197170
90000: 166476858
89000: 1658807720
88000: 3430520531
87000: 2946861093
86000: 3000600326
85000: 300034452
84000: 2813719249
83000: 3009927425
82000: 1127728469
81000: 2667791855
80000: 2632316050
79000: 2180301200
78000: 418999983
77000: 4254858933
76000: 2728734498
75000: 1863202698
74000: 4226419921
73000: 1917572494
72000: 3117082625
71000: 1032601538
70000: 2992135524
69000: 670119660
68000: 638731522
67000: 1460114012
66000: 1232274665
65000: 3667669961
64000: 191277965
63000: 3868442802
62000: 700664540
61000: 2271087482
60000: 3274078227
59000: 159900296
58000: 2778747772
57000: 2788477153
56000: 3965957780
55000: 2276993918
54000: 1986966104
53000: 3416414682
52000: 2162594060
51000: 2947744069
50000: 4024793290
49000: 631161701
48000: 728285173
47000: 1487641693
46000: 4049519424
45000: 613160608
44000: 1566126172
43000: 3731725133
42000: 2746368727
41000: 4168967735
40000: 1319649932
39000: 2964978784
38000: 967937134
37000: 3116555742
36000: 2279790642
35000: 2852914953
34000: 1040410911
33000: 226200467
32000: 1765748697
31000: 1418838964
30000: 1362983292
29000: 2877029789
28000: 583076938
27000: 2797138728
26000: 3033567067
25000: 3902265889
24000: 3287868661
23000: 2411740885
22000: 2747756860
21000: 1889759908
20000: 2975722149
19000: 3027693370
18000: 2418258302
17000: 490864179
16000: 1944489573
15000: 4212838860
14000: 1782397962
13000: 1981080238
12000: 1213651424
11000: 1407527546
10000: 661520991
9000: 143129551
8000: 3293448370
7000: 764314400
6000: 2246553770
5000: 2459308892
4000: 3776833152
3000: 2208260083
2000: 2845746745
1000: 2068042552
0: 290958364
Exiting @ tick 464394627000 because target called exit()

167
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,167 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.464395 # Number of seconds simulated
sim_ticks 464394627000 # Number of ticks simulated
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2996785 # Simulator instruction rate (inst/s)
host_op_rate 2996785 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1498717563 # Simulator tick rate (ticks/s)
host_mem_usage 251436 # Number of bytes of host memory used
host_seconds 309.86 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory
system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory
system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory
system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 237510597 # DTB read hits
system.cpu.dtb.read_misses 194650 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
system.cpu.dtb.write_hits 98301200 # DTB write hits
system.cpu.dtb.write_misses 6871 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
system.cpu.dtb.data_hits 335811797 # DTB hits
system.cpu.dtb.data_misses 201521 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 336013318 # DTB accesses
system.cpu.itb.fetch_hits 928789150 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 928789255 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 464394627000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 928789255 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928587629 # Number of instructions committed
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
system.cpu.num_int_insts 822136244 # number of integer instructions
system.cpu.num_fp_insts 33439365 # number of float instructions
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
system.cpu.num_mem_refs 336013318 # number of memory refs
system.cpu.num_load_insts 237705247 # Number of load instructions
system.cpu.num_store_insts 98308071 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 928789255 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 123111018 # Number of branches fetched
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction
system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction
system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 928789150 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution
system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution
system.membus.trans_dist::WriteReq 98301200 # Transaction distribution
system.membus.trans_dist::WriteResp 98301200 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1264600947 # Request fanout histogram
---------- End Simulation Statistics ----------

366
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -1,366 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,7 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)
warn: ignoring syscall sigprocmask(1, ...)

653
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
View file

@ -1,653 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51
gem5 started Jul 21 2016 14:09:29
gem5 executing on e108600-lin, pid 4305
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
634000: 545393176
633000: 3107247613
632000: 897887463
631000: 806367477
630000: 1682157095
629000: 1188376072
628000: 4076707785
627000: 3521684454
626000: 3144526095
625000: 1399223384
624000: 3380494826
623000: 4086509498
622000: 1473819475
621000: 638751284
620000: 3149483163
619000: 1489851375
618000: 1447059134
617000: 136329498
616000: 1288452788
615000: 3949816816
614000: 318984246
613000: 1019963195
612000: 2875280299
611000: 2997394777
610000: 4014932807
609000: 2291235006
608000: 355450951
607000: 201970399
606000: 3626124461
605000: 2207253273
604000: 2243886712
603000: 46791684
602000: 3176322294
601000: 1120582847
600000: 411705454
599000: 3162380308
598000: 2732375303
597000: 1376844609
596000: 3003023122
595000: 3869968535
594000: 1327286554
593000: 160655029
592000: 2038558826
591000: 3948772976
590000: 439262378
589000: 329537197
588000: 3678661972
587000: 4240182727
586000: 2283602206
585000: 1129811410
584000: 2831949168
583000: 1224559023
582000: 3161562107
581000: 2695467835
580000: 1234192577
579000: 1974816198
578000: 449576701
577000: 1424873035
576000: 2370444290
575000: 1743089134
574000: 2624046998
573000: 2071148441
572000: 2449219691
571000: 3774476172
570000: 1111630327
569000: 121721805
568000: 2981212266
567000: 3811833647
566000: 3676851843
565000: 1766252334
564000: 1622887950
563000: 1684409857
562000: 1686489387
561000: 610219569
560000: 2705092362
559000: 108031723
558000: 1316736987
557000: 2434129258
556000: 1411819652
555000: 1173886179
554000: 3044539233
553000: 151590417
552000: 3759426289
551000: 3451520306
550000: 294242855
549000: 890241051
548000: 876385779
547000: 119864600
546000: 3065674956
545000: 1670853168
544000: 997261561
543000: 660227344
542000: 3132294889
541000: 521956271
540000: 1133928405
539000: 3838154786
538000: 58624572
537000: 3544030439
536000: 432804999
535000: 1021857051
534000: 2644812356
533000: 773094580
532000: 901027171
531000: 3976696839
530000: 4167278216
529000: 504481120
528000: 320399857
527000: 638048690
526000: 3348998474
525000: 2660662065
524000: 2641437803
523000: 626927006
522000: 4063917554
521000: 3212249308
520000: 2561025301
519000: 1078140141
518000: 653939181
517000: 2154098204
516000: 3773089676
515000: 2568381435
514000: 3838886937
513000: 941125346
512000: 1318900410
511000: 297013287
510000: 241723934
509000: 1835499795
508000: 2309451230
507000: 1174814430
506000: 3615943386
505000: 51034971
504000: 3950453295
503000: 4186097241
502000: 327518343
501000: 3052462710
500000: 1586937404
499000: 2169094819
498000: 3613195151
497000: 817359591
496000: 1470916579
495000: 2091261583
494000: 2080080890
493000: 1772858697
492000: 2085609872
491000: 3280632925
490000: 1689322569
489000: 2947406469
488000: 765163324
487000: 3122594732
486000: 3385418480
485000: 1712345567
484000: 3675825158
483000: 1558929764
482000: 2672493410
481000: 3822528440
480000: 3741769935
479000: 2794026235
478000: 2541364185
477000: 3964482316
476000: 1202478165
475000: 4027617791
474000: 1905026738
473000: 2573787636
472000: 1170529797
471000: 2272525618
470000: 820833429
469000: 3219769529
468000: 2121197441
467000: 269331764
466000: 3038487237
465000: 2462675338
464000: 2703163101
463000: 547052037
462000: 3454526671
461000: 2124641794
460000: 1043737466
459000: 1785834964
458000: 3312335313
457000: 1213835042
456000: 3099430685
455000: 3003350806
454000: 3646781335
453000: 1474165966
452000: 705795987
451000: 2723908407
450000: 1323056304
449000: 1157256530
448000: 4077983523
447000: 3189085703
446000: 2241002747
445000: 3229050072
444000: 3500150226
443000: 1290722604
442000: 1866107725
441000: 4238277470
440000: 847346408
439000: 2474557496
438000: 2243092317
437000: 706909230
436000: 1303503693
435000: 1456129560
434000: 1073061079
433000: 692226634
432000: 186498656
431000: 2203415525
430000: 2183000701
429000: 1007776545
428000: 941117387
427000: 3805851413
426000: 1474193180
425000: 4231673903
424000: 2622576664
423000: 388097625
422000: 1165097488
421000: 3226044518
420000: 2531461570
419000: 1509806310
418000: 2667519114
417000: 1751592438
416000: 1286773513
415000: 1098182293
414000: 2111912709
413000: 1230737431
412000: 4090873946
411000: 3998652133
410000: 2486660396
409000: 2120483596
408000: 587404533
407000: 188697995
406000: 3265346093
405000: 4234961905
404000: 1211873901
403000: 4265173305
402000: 2208355316
401000: 3315952806
400000: 3917328941
399000: 2523594649
398000: 3805986783
397000: 2624925960
396000: 3716020189
395000: 2016201122
394000: 912930261
393000: 596904160
392000: 3571173642
391000: 2290782861
390000: 1162492227
389000: 1738718380
388000: 2599667355
387000: 2382332909
386000: 1471269037
385000: 2238392684
384000: 4034826126
383000: 1378654892
382000: 3702601850
381000: 397206179
380000: 2437704230
379000: 4187604139
378000: 779452169
377000: 2010372403
376000: 531902409
375000: 1371470602
374000: 4137796987
373000: 567426549
372000: 3082742955
371000: 2271575596
370000: 759731212
369000: 4063369437
368000: 299356452
367000: 536656228
366000: 3014961694
365000: 3016542135
364000: 2841873124
363000: 524434057
362000: 2887828889
361000: 3865529589
360000: 671363647
359000: 3104594256
358000: 1502485940
357000: 1776624159
356000: 4222478488
355000: 4127624139
354000: 2439477793
353000: 1593794891
352000: 591275342
351000: 2177291538
350000: 1923444781
349000: 758084193
348000: 775471359
347000: 191356974
346000: 494488375
345000: 1990489399
344000: 124118372
343000: 2046377904
342000: 1395427716
341000: 1342299790
340000: 38145994
339000: 2291884417
338000: 351940574
337000: 3984301480
336000: 2468666235
335000: 371500747
334000: 969922131
333000: 240854580
332000: 1644465214
331000: 1539846168
330000: 940087216
329000: 1491329232
328000: 2281687201
327000: 3030170550
326000: 3648503863
325000: 2037898355
324000: 174369956
323000: 2433605668
322000: 2334905107
321000: 1597704047
320000: 302297707
319000: 3209203690
318000: 3894539879
317000: 2868907580
316000: 2808087076
315000: 4034586233
314000: 3694191694
313000: 2001671958
312000: 559582279
311000: 3043016195
310000: 2785098502
309000: 4104602138
308000: 966154914
307000: 2446376687
306000: 789956605
305000: 1708137092
304000: 1733063901
303000: 2924555399
302000: 971356234
301000: 481382543
300000: 2647080988
299000: 4065744916
298000: 921140
297000: 654346784
296000: 485492098
295000: 217516816
294000: 4050820137
293000: 534726686
292000: 1686691079
291000: 1316587195
290000: 3746020838
289000: 1641967381
288000: 3492475215
287000: 3154885393
286000: 3686450617
285000: 3589739293
284000: 3558041700
283000: 4130142319
282000: 3132446063
281000: 982677436
280000: 799322395
279000: 151715214
278000: 3765942871
277000: 1712470933
276000: 3807622752
275000: 4163730108
274000: 1633425299
273000: 1654241631
272000: 1131025394
271000: 1375475855
270000: 553294237
269000: 4091487177
268000: 2841855980
267000: 2997369904
266000: 454385594
265000: 3757482634
264000: 3856197465
263000: 1084605457
262000: 2552759023
261000: 3786548799
260000: 272762545
259000: 2670277860
258000: 76233700
257000: 476168167
256000: 8969192
255000: 1998841030
254000: 1240074303
253000: 1771564446
252000: 710374418
251000: 821383716
250000: 3157726088
249000: 3083379502
248000: 2563632690
247000: 33723341
246000: 3303336748
245000: 4110677892
244000: 3811702913
243000: 53856215
242000: 243571468
241000: 52177779
240000: 46805590
239000: 1622010618
238000: 1321640849
237000: 3106837291
236000: 4102944642
235000: 137904396
234000: 339510135
233000: 88415957
232000: 3157666382
231000: 2571005912
230000: 3586247649
229000: 4172761781
228000: 2463305780
227000: 956927307
226000: 2169861547
225000: 1751989251
224000: 673059158
223000: 2782464516
222000: 3741392140
221000: 2856154963
220000: 3778376854
219000: 1538476717
218000: 2879698522
217000: 3734645735
216000: 1899042577
215000: 371356008
214000: 2416663698
213000: 1595919347
212000: 2816045438
211000: 132438808
210000: 1098603890
209000: 834913667
208000: 2707567283
207000: 3154122448
206000: 3696516104
205000: 1427952551
204000: 280496321
203000: 1185678745
202000: 3461951699
201000: 1369208434
200000: 3900136261
199000: 870818876
198000: 327248310
197000: 3116959470
196000: 1544241188
195000: 1568248814
194000: 2978831302
193000: 205660429
192000: 1704239501
191000: 3570135474
190000: 3878512103
189000: 1212729210
188000: 1873588815
187000: 324853813
186000: 432676298
185000: 1641364437
184000: 1568401301
183000: 525792402
182000: 861154382
181000: 2357325066
180000: 3626762590
179000: 4172125462
178000: 2108738993
177000: 2084782857
176000: 3956924509
175000: 17183073
174000: 3676839474
173000: 458250029
172000: 2635215219
171000: 1801029767
170000: 3602628987
169000: 370704281
168000: 177963345
167000: 924067814
166000: 3577678376
165000: 3717789117
164000: 3285809386
163000: 3738962897
162000: 3172510171
161000: 417992786
160000: 2591600214
159000: 3315096579
158000: 3590763949
157000: 198872871
156000: 2960653534
155000: 2246563682
154000: 2304045306
153000: 2647353543
152000: 2043381015
151000: 3952056867
150000: 2644058641
149000: 3477151018
148000: 1740210241
147000: 3314851112
146000: 1604832482
145000: 2572410736
144000: 1965059167
143000: 889666293
142000: 1024747903
141000: 226685285
140000: 3149168519
139000: 403638872
138000: 1725889104
137000: 1417402331
136000: 422304488
135000: 2595894054
134000: 4266597695
133000: 1116326556
132000: 3537080833
131000: 2181246909
130000: 1241997223
129000: 628191304
128000: 3074132403
127000: 2112958836
126000: 1371260930
125000: 2272975771
124000: 1379085607
123000: 1998991877
122000: 2760271255
121000: 3784187756
120000: 311188417
119000: 1123593459
118000: 1249155194
117000: 908703020
116000: 3765244393
115000: 3040869794
114000: 437536659
113000: 3343598822
112000: 2419089776
111000: 1263143640
110000: 1384687523
109000: 1727931349
108000: 2861733388
107000: 963829093
106000: 431354627
105000: 3568623360
104000: 2957399361
103000: 1071045618
102000: 3968457714
101000: 3448338394
100000: 2586060251
99000: 3401651822
98000: 1579089478
97000: 3722618916
96000: 759319595
95000: 1269278712
94000: 150489448
93000: 390013662
92000: 3663029784
91000: 555197170
90000: 166476858
89000: 1658807720
88000: 3430520531
87000: 2946861093
86000: 3000600326
85000: 300034452
84000: 2813719249
83000: 3009927425
82000: 1127728469
81000: 2667791855
80000: 2632316050
79000: 2180301200
78000: 418999983
77000: 4254858933
76000: 2728734498
75000: 1863202698
74000: 4226419921
73000: 1917572494
72000: 3117082625
71000: 1032601538
70000: 2992135524
69000: 670119660
68000: 638731522
67000: 1460114012
66000: 1232274665
65000: 3667669961
64000: 191277965
63000: 3868442802
62000: 700664540
61000: 2271087482
60000: 3274078227
59000: 159900296
58000: 2778747772
57000: 2788477153
56000: 3965957780
55000: 2276993918
54000: 1986966104
53000: 3416414682
52000: 2162594060
51000: 2947744069
50000: 4024793290
49000: 631161701
48000: 728285173
47000: 1487641693
46000: 4049519424
45000: 613160608
44000: 1566126172
43000: 3731725133
42000: 2746368727
41000: 4168967735
40000: 1319649932
39000: 2964978784
38000: 967937134
37000: 3116555742
36000: 2279790642
35000: 2852914953
34000: 1040410911
33000: 226200467
32000: 1765748697
31000: 1418838964
30000: 1362983292
29000: 2877029789
28000: 583076938
27000: 2797138728
26000: 3033567067
25000: 3902265889
24000: 3287868661
23000: 2411740885
22000: 2747756860
21000: 1889759908
20000: 2975722149
19000: 3027693370
18000: 2418258302
17000: 490864179
16000: 1944489573
15000: 4212838860
14000: 1782397962
13000: 1981080238
12000: 1213651424
11000: 1407527546
10000: 661520991
9000: 143129551
8000: 3293448370
7000: 764314400
6000: 2246553770
5000: 2459308892
4000: 3776833152
3000: 2208260083
2000: 2845746745
1000: 2068042552
0: 290958364
Exiting @ tick 1288319411500 because target called exit()

571
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,571 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.288611 # Number of seconds simulated
sim_ticks 1288611150500 # Number of ticks simulated
final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2016883 # Simulator instruction rate (inst/s)
host_op_rate 2016883 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2798849858 # Simulator tick rate (ticks/s)
host_mem_usage 261432 # Number of bytes of host memory used
host_seconds 460.41 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory
system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory
system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 237510597 # DTB read hits
system.cpu.dtb.read_misses 194650 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
system.cpu.dtb.write_hits 98301200 # DTB write hits
system.cpu.dtb.write_misses 6871 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
system.cpu.dtb.data_hits 335811797 # DTB hits
system.cpu.dtb.data_misses 201521 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 336013318 # DTB accesses
system.cpu.itb.fetch_hits 928789151 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 928789256 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2577222301 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928587629 # Number of instructions committed
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
system.cpu.num_int_insts 822136244 # number of integer instructions
system.cpu.num_fp_insts 33439365 # number of float instructions
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
system.cpu.num_mem_refs 336013318 # number of memory refs
system.cpu.num_load_insts 237705247 # Number of load instructions
system.cpu.num_store_insts 98308071 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 2577222301 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 123111018 # Number of branches fetched
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction
system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction
system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 928789150 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 776432 # number of replacements
system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks
system.cpu.dcache.writebacks::total 88841 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 4618 # number of replacements
system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits
system.cpu.icache.overall_hits::total 928782983 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
system.cpu.icache.overall_misses::total 6168 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 4618 # number of writebacks
system.cpu.icache.writebacks::total 4618 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 258865 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits
system.cpu.l2cache.overall_hits::total 495300 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses
system.cpu.l2cache.overall_misses::total 291396 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14607390000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 258865 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 224748 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
system.membus.trans_dist::CleanEvict 190457 # Transaction distribution
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 291396 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 291396 # Request fanout histogram
system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

877
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
View file

@ -1,877 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr
View file

@ -1,7 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

14
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
View file

@ -1,14 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 28063
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 61709224000 because target called exit()

829
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,829 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.061709 # Number of seconds simulated
sim_ticks 61709224000 # Number of ticks simulated
final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 484192 # Simulator instruction rate (inst/s)
host_op_rate 484192 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 337853764 # Simulator tick rate (ticks/s)
host_mem_usage 263376 # Number of bytes of host memory used
host_seconds 182.65 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory
system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory
system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 165740 # Number of read requests accepted
system.physmem.writeReqs 115251 # Number of write requests accepted
system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue
system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10345 # Per bank write bursts
system.physmem.perBankRdBursts::1 10387 # Per bank write bursts
system.physmem.perBankRdBursts::2 10224 # Per bank write bursts
system.physmem.perBankRdBursts::3 10068 # Per bank write bursts
system.physmem.perBankRdBursts::4 10353 # Per bank write bursts
system.physmem.perBankRdBursts::5 10360 # Per bank write bursts
system.physmem.perBankRdBursts::6 9794 # Per bank write bursts
system.physmem.perBankRdBursts::7 10230 # Per bank write bursts
system.physmem.perBankRdBursts::8 10568 # Per bank write bursts
system.physmem.perBankRdBursts::9 10626 # Per bank write bursts
system.physmem.perBankRdBursts::10 10568 # Per bank write bursts
system.physmem.perBankRdBursts::11 10241 # Per bank write bursts
system.physmem.perBankRdBursts::12 10306 # Per bank write bursts
system.physmem.perBankRdBursts::13 10592 # Per bank write bursts
system.physmem.perBankRdBursts::14 10494 # Per bank write bursts
system.physmem.perBankRdBursts::15 10573 # Per bank write bursts
system.physmem.perBankWrBursts::0 7166 # Per bank write bursts
system.physmem.perBankWrBursts::1 7281 # Per bank write bursts
system.physmem.perBankWrBursts::2 7303 # Per bank write bursts
system.physmem.perBankWrBursts::3 7012 # Per bank write bursts
system.physmem.perBankWrBursts::4 7145 # Per bank write bursts
system.physmem.perBankWrBursts::5 7305 # Per bank write bursts
system.physmem.perBankWrBursts::6 6890 # Per bank write bursts
system.physmem.perBankWrBursts::7 7164 # Per bank write bursts
system.physmem.perBankWrBursts::8 7246 # Per bank write bursts
system.physmem.perBankWrBursts::9 7071 # Per bank write bursts
system.physmem.perBankWrBursts::10 7213 # Per bank write bursts
system.physmem.perBankWrBursts::11 7126 # Per bank write bursts
system.physmem.perBankWrBursts::12 7072 # Per bank write bursts
system.physmem.perBankWrBursts::13 7397 # Per bank write bursts
system.physmem.perBankWrBursts::14 7351 # Per bank write bursts
system.physmem.perBankWrBursts::15 7483 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 61709200500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 165740 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 115251 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads
system.physmem.totQLat 3617300750 # Total ticks spent queuing
system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers
system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.28 # Data bus utilization in percentage
system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing
system.physmem.readRowHits 144262 # Number of row buffer hits during reads
system.physmem.writeRowHits 89468 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes
system.physmem.avgGap 219612.73 # Average gap between requests
system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ)
system.physmem_0.averagePower 393.299410 # Core power per rank (mW)
system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states
system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states
system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ)
system.physmem_1.averagePower 400.858918 # Core power per rank (mW)
system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states
system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 14696527 # Number of BP lookups
system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20579387 # DTB read hits
system.cpu.dtb.read_misses 95377 # DTB read misses
system.cpu.dtb.read_acv 10 # DTB read access violations
system.cpu.dtb.read_accesses 20674764 # DTB read accesses
system.cpu.dtb.write_hits 14666029 # DTB write hits
system.cpu.dtb.write_misses 8840 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14674869 # DTB write accesses
system.cpu.dtb.data_hits 35245416 # DTB hits
system.cpu.dtb.data_misses 104217 # DTB misses
system.cpu.dtb.data_acv 10 # DTB access violations
system.cpu.dtb.data_accesses 35349633 # DTB accesses
system.cpu.itb.fetch_hits 25650137 # ITB hits
system.cpu.itb.fetch_misses 5179 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25655316 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 123418448 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88438073 # Number of instructions committed
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.395535 # CPI: cycles per instruction
system.cpu.ipc 0.716571 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction
system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction
system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.40% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction
system.cpu.op_class_0::MemRead 20366476 23.03% 83.47% # Class of committed instruction
system.cpu.op_class_0::MemWrite 14619024 16.53% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 310 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 88438073 # Class of committed instruction
system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked
system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 200809 # number of replacements
system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits
system.cpu.dcache.overall_hits::total 34647996 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses
system.cpu.dcache.overall_misses::total 341611 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 168117 # number of writebacks
system.cpu.dcache.writebacks::total 168117 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136509 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 136509 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 136706 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 136706 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 136706 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 136706 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61338 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61338 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204905 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204905 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204905 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204905 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3088657500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50354.714859 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50354.714859 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84853.890518 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84853.890518 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 153962 # number of replacements
system.cpu.icache.tags.tagsinuse 1929.475732 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25494126 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 156010 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 163.413409 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 43906590500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1929.475732 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.942127 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.942127 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 51456284 # Number of tag accesses
system.cpu.icache.tags.data_accesses 51456284 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 25494126 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25494126 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25494126 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25494126 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25494126 # number of overall hits
system.cpu.icache.overall_hits::total 25494126 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 156011 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 156011 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 156011 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 156011 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 156011 # number of overall misses
system.cpu.icache.overall_misses::total 156011 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2690499000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2690499000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2690499000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2690499000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2690499000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2690499000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25650137 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25650137 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25650137 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25650137 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25650137 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25650137 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17245.572428 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17245.572428 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17245.572428 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17245.572428 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 153962 # number of writebacks
system.cpu.icache.writebacks::total 153962 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 156011 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 156011 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 156011 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 156011 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 156011 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 156011 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2534489000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2534489000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2534489000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2534489000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2534489000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2534489000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 135280 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31691.220276 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 547521 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 168048 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.258123 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 14447297000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 710.430921 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1986.776331 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 28994.013023 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.021681 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060632 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.884827 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.967139 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 8856 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22759 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 5893544 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 5893544 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 168117 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 168117 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 153962 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 153962 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149161 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 149161 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 149161 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 195175 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 149161 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits
system.cpu.l2cache.overall_hits::total 195175 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6850 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 6850 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27983 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 27983 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 6850 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 158891 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 165741 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 6850 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158891 # number of overall misses
system.cpu.l2cache.overall_misses::total 165741 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11833894500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 11833894500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 734127500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 734127500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2646160500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2646160500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 734127500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 14480055000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 15214182500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 734127500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 14480055000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 15214182500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168117 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 168117 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 153962 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 153962 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 156011 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 156011 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61338 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 61338 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 156011 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204905 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 360916 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 156011 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204905 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 360916 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043907 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043907 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456210 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456210 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043907 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775437 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.459223 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043907 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775437 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.459223 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90398.558530 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 115252 # number of writebacks
system.cpu.l2cache.writebacks::total 115252 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 135280 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 34832 # Transaction distribution
system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution
system.membus.trans_dist::CleanEvict 15886 # Transaction distribution
system.membus.trans_dist::ReadExReq 130908 # Transaction distribution
system.membus.trans_dist::ReadExResp 130908 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 165740 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 165740 # Request fanout histogram
system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.4 # Layer utilization (%)
---------- End Simulation Statistics ----------

825
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,825 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,7 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

14
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -1,14 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:44
gem5 executing on e108600-lin, pid 28054
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 22819771500 because target called exit()

158
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
View file

@ -1,158 +0,0 @@
SYSTEM TYPE...
__ZTC__ := False
__UNIX__ := True
__RISC__ := True
SPEC_CPU2000_LP64 := True
__MAC__ := False
__BCC__ := False
__BORLANDC__ := False
__GUI__ := False
__WTC__ := False
__HP__ := False
CODE OPTIONS...
__MACROIZE_HM__ := True
__MACROIZE_MEM__ := True
ENV01 := True
USE_HPP_STYPE_HDRS := False
USE_H_STYPE_HDRS := False
CODE INCLUSION PARAMETERS...
INCLUDE_ALL_CODE := False
INCLUDE_DELETE_CODE := True
__SWAP_GRP_POS__ := True
__INCLUDE_MTRX__ := False
__BAD_CODE__ := False
API_INCLUDE := False
BE_CAREFUL := False
OLDWAY := False
NOTUSED := False
SYSTEM PARAMETERS...
EXT_ENUM := 999999999L
CHUNK_CONSTANT := 55555555
CORE_CONSTANT := 55555555
CORE_LIMIT := 20971520
CorePage_Size := 384000
ALIGN_BYTES := True
CORE_BLOCK_ALIGN := 8
FAR_MEM := False
MEMORY MANAGEMENT PARAMETERS...
SYSTEM_ALLOC := True
SYSTEM_FREESTORE := True
__NO_DISKCACHE__ := False
__FREEZE_VCHUNKS__ := True
__FREEZE_GRP_PACKETS__ := True
__MINIMIZE_TREE_CACHE__:= True
SYSTEM STD PARAMETERS...
__STDOUT__ := False
NULL := 0
LPTR := False
False_Status := 1
True_Status := 0
LARGE := True
TWOBYTE_BOOL := False
__NOSTR__ := False
MEMORY VALIDATION PARAMETERS...
CORE_CRC_CHECK := False
VALIDATE_MEM_CHUNKS := False
SYSTEM DEBUG OPTIONS...
DEBUG := False
MCSTAT := False
TRACKBACK := False
FLUSH_FILES := False
DEBUG_CORE0 := False
DEBUG_RISC := False
__TREE_BUG__ := False
__TRACK_FILE_READS__ := False
PAGE_SPACE := False
LEAVE_NO_TRACE := True
NULL_TRACE_STRS := False
TIME PARAMETERS...
CLOCK_IS_LONG := False
__DISPLAY_TIME__ := False
__TREE_TIME__ := False
__DISPLAY_ERRORS__ := False
API MACROS...
__BMT01__ := True
OPTIMIZE := True
END OF DEFINES.
... IMPLODE MEMORY ...
SWAP to DiskCache := False
FREEZE_GRP_PACKETS:= True
QueBug := 1000
sizeof(boolean) = 4
sizeof(sizetype) = 4
sizeof(chunkstruc) = 32
sizeof(shorttype ) = 2
sizeof(idtype ) = 2
sizeof(sizetype ) = 4
sizeof(indextype ) = 4
sizeof(numtype ) = 4
sizeof(handletype) = 4
sizeof(tokentype ) = 8
sizeof(short ) = 2
sizeof(int ) = 4
sizeof(lt64 ) = 4
sizeof(farlongtype) = 4
sizeof(long ) = 8
sizeof(longaddr ) = 8
sizeof(float ) = 4
sizeof(double ) = 8
sizeof(addrtype ) = 8
sizeof(char * ) = 8
ALLOC CORE_1 :: 16
BHOOLE NATH
OPEN File ./input/lendian.rnv
*Status = 0
DB HDR restored from FileVbn[ 0]
DB BlkDirOffset : @ 2030c0
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
DB Handle Chunk's StackPtr = 20797
DB[ 1] LOADED; Handles= 20797
KERNEL in CORE[ 1] Restored @ 4005c800
OPEN File ./input/lendian.wnv
*Status = 0
DB HDR restored from FileVbn[ 0]
DB BlkDirOffset : @ 21c40
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
DB Handle Chunk's StackPtr = 17
DB[ 2] LOADED; Handles= 17
VORTEx_Status == -8 || fffffff8
BE HERE NOW !!!
... VORTEx ON LINE ...
... END OF SESSION ...

258
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
View file

@ -1,258 +0,0 @@
CREATE Db Header and Db Primal ...
NEW DB [ 3] Created.
VORTEX INPUT PARAMETERS::
MESSAGE FileName: smred.msg
OUTPUT FileName: smred.out
DISK CACHE FileName: NULL
PART DB FileName: parts.db
DRAW DB FileName: draw.db
PERSON DB FileName: emp.db
PERSONS Data FileName: ./input/persons.250
PARTS Count : 100
OUTER Loops : 1
INNER Loops : 1
LOOKUP Parts : 25
DELETE Parts : 10
STUFF Parts : 10
DEPTH Traverse: 5
% DECREASE Parts : 0
% INCREASE LookUps : 0
% INCREASE Deletes : 0
% INCREASE Stuffs : 0
FREEZE_PACKETS : 1
ALLOC_CHUNKS : 10000
EXTEND_CHUNKS : 5000
DELETE Draw objects : True
DELETE Part objects : False
QUE_BUG : 1000
VOID_BOUNDARY : 67108864
VOID_RESERVE : 1048576
COMMIT_DBS : False
BMT TEST :: files...
EdbName := PartLib
EdbFileName := parts.db
DrwName := DrawLib
DrwFileName := draw.db
EmpName := PersonLib
EmpFileName := emp.db
Swap to DiskCache := False
Freeze the cache := True
BMT TEST :: parms...
DeBug modulo := 1000
Create Parts count:= 100
Outer Loops := 1
Inner Loops := 1
Look Ups := 25
Delete Parts := 10
Stuff Parts := 10
Traverse Limit := 5
Delete Draws := True
Delete Parts := False
Delete ALL Parts := after every <mod 0>Outer Loop
INITIALIZE LIBRARY ::
INITIALIZE SCHEMA ::
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 4] Created.
PartLibCreate:: Db[ 4]; VpartsDir= 1
Part Count= 1
Initialize the Class maps
LIST HEADS loaded ... DbListHead_Class = 207
DbListNode_Class = 206
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 5] Created.
DrawLibCreate:: Db[ 5]; VpartsDir= 1
Initialize the Class maps of this schema.
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 6] Created.
***NOTE*** Persons Library Extended!
Create <131072> Persons.
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
LAST Person Read::
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
BUILD <Query0> for <Part2> class::
if (link[1].length >= 5) ::
Build Query2 for <Address> class::
if (State == CA || State == T*)
Build Query1 for <Person> class::
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
BUILD <Query3> for <DrawObj> class::
if (Id >= 3000
&& (Id >= 3000 && Id <= 3001)
&& Id >= 3002)
BUILD <Query4> for <NamedDrawObj> class::
if (Nam == Pre*
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
&& Id <= 7)
SEED := 1008; Swap = False; RgnEntries = 135
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
Create 100 New Parts
Create Part 1. Token[ 4: 2].
< 100> Parts Created. CurrentId= 100
Connect each instantiated Part TO 3 unique Parts
Connect Part 1. Token[ 4: 2]
Connect Part 25. Token[ 4: 26] FromList= 26.
Connect Part 12. Token[ 4: 13] FromList= 13.
Connect Part 59. Token[ 4: 60] FromList= 60.
SET <DrawObjs> entries::
1. [ 5: 5] := <1 >; @[: 6]
Iteration count = 100
SET <NamedDrawObjs> entries::
1. [ 5: 39] := <14 >;
Iteration count = 12
SET <LibRectangles> entries::
1. [ 5: 23] := <8 >; @[: 24]
Iteration count = 12
LIST <DbRectangles> entries::
1. [ 5: 23]
Iteration count = 12
SET <PersonNames > entries::
Iteration count = 250
COMMIT All Image copies:: Release=<True>; Max Parts= 100
< 100> Part images' Committed.
< 0> are Named.
< 50> Point images' Committed.
< 81> Person images' Committed.
COMMIT Parts(* 100)
Commit TestObj_Class in <Primal> DB.
ItNum 0. Token[ 0: 0]. TestObj Committed.
< 0> TestObj images' Committed.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
< 0> CartesianPoint images' Committed.
BEGIN Inner Loop Sequence::.
INNER LOOP [ 1: 1] :
LOOK UP 25 Random Parts and Export each Part.
LookUp for 26 parts; Asserts = 8
<Part2 > Asserts = 2; NULL Asserts = 3.
<DrawObj > Asserts = 0; NULL Asserts = 5.
<NamedObj > Asserts = 0; NULL Asserts = 0.
<Person > Asserts = 0; NULL Asserts = 5.
<TestObj > Asserts = 60; NULL Asserts = 0.
DELETE 10 Random Parts.
PartDelete :: Token[ 4: 91].
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
Vlists[ 89] := 100;
Delete for 11 parts;
Traverse Count= 0
TRAVERSE PartId[ 6] and all Connections to 5 Levels
SEED In Traverse Part [ 4: 65] @ Level = 4.
Traverse Count= 357
Traverse Asserts = 5. True Tests = 1
< 5> DrawObj objects DELETED.
< 2> are Named.
< 2> Point objects DELETED.
CREATE 10 Additional Parts
Create 10 New Parts
Create Part 101. Token[ 4: 102].
< 10> Parts Created. CurrentId= 110
Connect each instantiated Part TO 3 unique Parts
COMMIT All Image copies:: Release=<True>; Max Parts= 110
< 81> Part images' Committed.
< 0> are Named.
< 38> Point images' Committed.
< 31> Person images' Committed.
COMMIT Parts(* 100)
Commit TestObj_Class in <Primal> DB.
ItNum 0. Token[ 3: 4]. TestObj Committed.
< 15> TestObj images' Committed.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
< 16> CartesianPoint images' Committed.
DELETE All TestObj objects;
Delete TestObj_Class in <Primal> DB.
ItNum 0. Token[ 3: 4]. TestObj Deleted.
< 15> TestObj objects Deleted.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
< 16> CartesianPoint objects Deleted.
DELETE TestObj and Point objects...
END INNER LOOP [ 1: 1].
DELETE All TestObj objects;
Delete TestObj_Class in <Primal> DB.
< 0> TestObj objects Deleted.
Commit CartesianPoint_Class in <Primal> DB.
< 0> CartesianPoint objects Deleted.
DELETE TestObj and Point objects...
STATUS= -201
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!

1097
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

877
tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
View file

@ -1,877 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr
View file

@ -1,7 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

29
tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout
View file

@ -1,29 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 28067
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1241902335500 because target called exit()

836
tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,836 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.241902 # Number of seconds simulated
sim_ticks 1241902335500 # Number of ticks simulated
final_tick 1241902335500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 473348 # Simulator instruction rate (inst/s)
host_op_rate 473348 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 321867657 # Simulator tick rate (ticks/s)
host_mem_usage 255296 # Number of bytes of host memory used
host_seconds 3858.43 # Real time elapsed on the host
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 126178240 # Number of bytes read from this memory
system.physmem.bytes_read::total 126239872 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 66092288 # Number of bytes written to this memory
system.physmem.bytes_written::total 66092288 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1971535 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1972498 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1032692 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1032692 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 49627 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 101600775 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 101650402 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 49627 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 49627 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 53218587 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 53218587 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 53218587 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 49627 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 101600775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 154868990 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1972498 # Number of read requests accepted
system.physmem.writeReqs 1032692 # Number of write requests accepted
system.physmem.readBursts 1972498 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1032692 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 126161536 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 78336 # Total number of bytes read from write queue
system.physmem.bytesWritten 66090880 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 126239872 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 66092288 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1224 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 119357 # Per bank write bursts
system.physmem.perBankRdBursts::1 114729 # Per bank write bursts
system.physmem.perBankRdBursts::2 116715 # Per bank write bursts
system.physmem.perBankRdBursts::3 118322 # Per bank write bursts
system.physmem.perBankRdBursts::4 118352 # Per bank write bursts
system.physmem.perBankRdBursts::5 118237 # Per bank write bursts
system.physmem.perBankRdBursts::6 120696 # Per bank write bursts
system.physmem.perBankRdBursts::7 125562 # Per bank write bursts
system.physmem.perBankRdBursts::8 127868 # Per bank write bursts
system.physmem.perBankRdBursts::9 130858 # Per bank write bursts
system.physmem.perBankRdBursts::10 129451 # Per bank write bursts
system.physmem.perBankRdBursts::11 131187 # Per bank write bursts
system.physmem.perBankRdBursts::12 126743 # Per bank write bursts
system.physmem.perBankRdBursts::13 125956 # Per bank write bursts
system.physmem.perBankRdBursts::14 123338 # Per bank write bursts
system.physmem.perBankRdBursts::15 123903 # Per bank write bursts
system.physmem.perBankWrBursts::0 62004 # Per bank write bursts
system.physmem.perBankWrBursts::1 62324 # Per bank write bursts
system.physmem.perBankWrBursts::2 61320 # Per bank write bursts
system.physmem.perBankWrBursts::3 62012 # Per bank write bursts
system.physmem.perBankWrBursts::4 62437 # Per bank write bursts
system.physmem.perBankWrBursts::5 63989 # Per bank write bursts
system.physmem.perBankWrBursts::6 65066 # Per bank write bursts
system.physmem.perBankWrBursts::7 66492 # Per bank write bursts
system.physmem.perBankWrBursts::8 66230 # Per bank write bursts
system.physmem.perBankWrBursts::9 66701 # Per bank write bursts
system.physmem.perBankWrBursts::10 66337 # Per bank write bursts
system.physmem.perBankWrBursts::11 66707 # Per bank write bursts
system.physmem.perBankWrBursts::12 65162 # Per bank write bursts
system.physmem.perBankWrBursts::13 65226 # Per bank write bursts
system.physmem.perBankWrBursts::14 65630 # Per bank write bursts
system.physmem.perBankWrBursts::15 65033 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1241902212500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1972498 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1032692 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1834002 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 137262 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 28680 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 29758 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 55879 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 61072 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 61319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 61406 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 61263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 61215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 61129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 61163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 61122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 61175 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 61200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 61213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 61359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 61719 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 61033 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 60943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1848577 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 103.999494 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.158472 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 130.975371 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1464855 79.24% 79.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 267102 14.45% 93.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 48426 2.62% 96.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20608 1.11% 97.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 12613 0.68% 98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7404 0.40% 98.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5582 0.30% 98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 4649 0.25% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 17338 0.94% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1848577 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 60747 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 32.448697 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 23.033030 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 139.766082 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 60580 99.73% 99.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 126 0.21% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4607 3 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 60747 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 60747 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.999523 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.968024 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.037878 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 30790 50.69% 50.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1097 1.81% 52.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 26995 44.44% 96.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 1834 3.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 26 0.04% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 60747 # Writes before turning the bus around for reads
system.physmem.totQLat 58523135000 # Total ticks spent queuing
system.physmem.totMemAccLat 95484522500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9856370000 # Total ticks spent in databus transfers
system.physmem.avgQLat 29687.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 48437.98 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 101.59 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 53.22 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 101.65 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 53.22 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.21 # Data bus utilization in percentage
system.physmem.busUtilRead 0.79 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing
system.physmem.readRowHits 727297 # Number of row buffer hits during reads
system.physmem.writeRowHits 428065 # Number of row buffer hits during writes
system.physmem.readRowHitRate 36.89 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 41.45 # Row buffer hit rate for writes
system.physmem.avgGap 413252.48 # Average gap between requests
system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6395269440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3399162525 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 6797065800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 2639461680 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 75004519200.000015 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 46893448560 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2685169920 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 246120093660 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 85384513440 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 94763106600 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 570117979365 # Total energy per rank (pJ)
system.physmem_0.averagePower 459.068285 # Core power per rank (mW)
system.physmem_0.totalIdleTime 1131989083250 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 3611832250 # Time in different power states
system.physmem_0.memoryStateTime::REF 31797904000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 369900280750 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 222356311250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 74502708250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 539733299000 # Time in different power states
system.physmem_1.actEnergy 6803606040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3616187190 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 7277830560 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 2751075720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 76383156720.000015 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 47598512910 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2658705600 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 254833635780 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 85755552000 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 89279622225 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 576994094775 # Total energy per rank (pJ)
system.physmem_1.averagePower 464.605041 # Core power per rank (mW)
system.physmem_1.totalIdleTime 1130512338500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 3468880500 # Time in different power states
system.physmem_1.memoryStateTime::REF 32377406000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 348347909000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 223320346000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 75543655250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 558844138750 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 246965199 # Number of BP lookups
system.cpu.branchPred.condPredicted 186917374 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15586746 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 168139701 # Number of BTB lookups
system.cpu.branchPred.BTBHits 165606683 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.493504 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 18556232 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 106082 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 63 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 251 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 453404968 # DTB read hits
system.cpu.dtb.read_misses 5001226 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 458406194 # DTB read accesses
system.cpu.dtb.write_hits 161377184 # DTB write hits
system.cpu.dtb.write_misses 1709229 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 163086413 # DTB write accesses
system.cpu.dtb.data_hits 614782152 # DTB hits
system.cpu.dtb.data_misses 6710455 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 621492607 # DTB accesses
system.cpu.itb.fetch_hits 600133421 # ITB hits
system.cpu.itb.fetch_misses 19 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 600133440 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2483804671 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1826378509 # Number of instructions committed
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
system.cpu.discardedOps 55133015 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.359962 # CPI: cycles per instruction
system.cpu.ipc 0.735315 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction
system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::MemRead 449492662 24.61% 91.11% # Class of committed instruction
system.cpu.op_class_0::MemWrite 162429751 8.89% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 55 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 1826378509 # Class of committed instruction
system.cpu.tickCycles 2082494897 # Number of cycles that the object actually ticked
system.cpu.idleCycles 401309774 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9121955 # number of replacements
system.cpu.dcache.tags.tagsinuse 4080.932596 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 602775567 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 66.049989 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 17009517500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4080.932596 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.996321 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.996321 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1466 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2515 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1233653477 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1233653477 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 444296125 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 444296125 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158479442 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 158479442 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 602775567 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 602775567 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 602775567 # number of overall hits
system.cpu.dcache.overall_hits::total 602775567 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7239086 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7239086 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2249060 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2249060 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9488146 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9488146 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9488146 # number of overall misses
system.cpu.dcache.overall_misses::total 9488146 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 201399177000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 201399177000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 119572112000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 119572112000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 320971289000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 320971289000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 320971289000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 320971289000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 451535211 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 451535211 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 612263713 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 612263713 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 612263713 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 612263713 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013993 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013993 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015497 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015497 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015497 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015497 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27821.078103 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27821.078103 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53165.372200 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53165.372200 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 33828.662523 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33828.662523 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3671979 # number of writebacks
system.cpu.dcache.writebacks::total 3671979 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 361730 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 361730 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 362095 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 362095 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 362095 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 362095 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238721 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7238721 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887330 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1887330 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9126051 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9126051 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9126051 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9126051 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194152625000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 194152625000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91149337000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 91149337000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285301962000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 285301962000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285301962000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 285301962000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26821.399112 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26821.399112 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48295.389254 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48295.389254 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 754.212981 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 600132458 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 623190.506750 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 754.212981 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.368268 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.368268 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 879 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1200267805 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1200267805 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 600132458 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 600132458 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 600132458 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 600132458 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 600132458 # number of overall hits
system.cpu.icache.overall_hits::total 600132458 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 963 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 963 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 963 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 963 # number of overall misses
system.cpu.icache.overall_misses::total 963 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 93461000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 93461000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 93461000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 93461000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 93461000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 93461000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 600133421 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 600133421 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 600133421 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 600133421 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 600133421 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 600133421 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 97051.921080 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 97051.921080 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 97051.921080 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 97051.921080 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
system.cpu.icache.writebacks::total 3 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 92498000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 92498000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 92498000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 92498000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92498000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 92498000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 96051.921080 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 96051.921080 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1940051 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31462.306469 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 16275911 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1972819 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 8.250078 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 89697966000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 7.975185 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.025867 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31412.305417 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000243 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001283 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.958627 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.960153 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2816 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7096 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21807 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 147964595 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 147964595 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3671979 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3671979 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1095271 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1095271 # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6059245 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6059245 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 7154516 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7154516 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7154516 # number of overall hits
system.cpu.l2cache.overall_hits::total 7154516 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 792059 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 792059 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 963 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 963 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1179476 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1179476 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1971535 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1972498 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1971535 # number of overall misses
system.cpu.l2cache.overall_misses::total 1972498 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76750433500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 76750433500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 91051000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 91051000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 119656496500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 119656496500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 91051000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 196406930000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 196497981000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 91051000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 196406930000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 196497981000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3671979 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3671979 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887330 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1887330 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 963 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 963 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238721 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7238721 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9126051 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9127014 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9126051 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9127014 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419672 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.419672 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162940 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162940 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.216034 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.216116 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.216034 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.216116 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96899.894452 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96899.894452 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 94549.325026 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 94549.325026 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101448.860765 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 101448.860765 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 99618.849297 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 99618.849297 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1032692 # number of writebacks
system.cpu.l2cache.writebacks::total 1032692 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792059 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 792059 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 963 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 963 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1179476 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1179476 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1971535 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1972498 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1971535 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1972498 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68829843500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68829843500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81421000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81421000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 107861736500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 107861736500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81421000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 176691580000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 176773001000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81421000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 176691580000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 176773001000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419672 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419672 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162940 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162940 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216116 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.216116 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86899.894452 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86899.894452 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 84549.325026 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 84549.325026 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 91448.860765 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 91448.860765 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18248972 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121958 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1442 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1442 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7239684 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4704671 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6357335 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1887330 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1887330 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238721 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374057 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27375986 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819073920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 819135744 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1940051 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 66092288 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 11067065 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.011414 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11065623 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1442 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11067065 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12796468000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13689076500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 3911349 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 1938851 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1180439 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1032692 # Transaction distribution
system.membus.trans_dist::CleanEvict 906159 # Transaction distribution
system.membus.trans_dist::ReadExReq 792059 # Transaction distribution
system.membus.trans_dist::ReadExResp 792059 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1180439 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883847 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5883847 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192332160 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 192332160 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1972498 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1972498 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1972498 # Request fanout histogram
system.membus.reqLayer0.occupancy 8507556000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 10783034500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------

825
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,825 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,7 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

29
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -1,29 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:44
gem5 executing on e108600-lin, pid 28058
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 684199968000 because target called exit()

1119
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

203
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -1,203 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

6
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,6 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

29
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,29 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51
gem5 started Jul 21 2016 14:09:29
gem5 executing on e108600-lin, pid 4310
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 913189263000 because target called exit()

167
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,167 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.913189 # Number of seconds simulated
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3052391 # Simulator instruction rate (inst/s)
host_op_rate 3052390 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1531729085 # Simulator tick rate (ticks/s)
host_mem_usage 242484 # Number of bytes of host memory used
host_seconds 596.18 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory
system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory
system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory
system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378509 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1826378527 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 214632552 # Number of branches fetched
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction
system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution
system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution
system.membus.trans_dist::WriteReq 160728502 # Transaction distribution
system.membus.trans_dist::WriteResp 160728502 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2431702674 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 2431702674 # Request fanout histogram
---------- End Simulation Statistics ----------

366
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -1,366 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

6
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,6 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

29
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
View file

@ -1,29 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 19 2016 12:23:51
gem5 started Jul 21 2016 14:09:29
gem5 executing on e108600-lin, pid 4312
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2636719559500 because target called exit()

566
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,566 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.639614 # Number of seconds simulated
sim_ticks 2639613874500 # Number of ticks simulated
final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2013574 # Simulator instruction rate (inst/s)
host_op_rate 2013574 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2920714569 # Simulator tick rate (ticks/s)
host_mem_usage 253500 # Number of bytes of host memory used
host_seconds 903.76 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory
system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory
system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378510 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5279227749 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5279227749 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 214632552 # Number of branches fetched
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction
system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9107638 # number of replacements
system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks
system.cpu.dcache.writebacks::total 3664823 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits
system.cpu.icache.overall_hits::total 1826377708 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.icache.overall_misses::total 802 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
system.cpu.icache.writebacks::total 1 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49739500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 49739500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49739500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 49739500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49739500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 49739500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62019.326683 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62019.326683 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1938767 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31260.683710 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 16248398 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1971535 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 8.241496 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 217871689000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8.109026 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.419408 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31214.155276 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000247 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001172 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.952580 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.954000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 664 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1281 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27794 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 147732935 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 147732935 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3664823 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3664823 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1095314 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1095314 # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046007 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6046007 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 7141321 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7141321 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7141321 # number of overall hits
system.cpu.l2cache.overall_hits::total 7141321 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 794006 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 794006 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176407 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1176407 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1970413 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1971215 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1970413 # number of overall misses
system.cpu.l2cache.overall_misses::total 1971215 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48037363000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 48037363000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48529000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 48529000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71172626500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 71172626500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 48529000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 119209989500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 119258518500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 48529000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 119209989500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 119258518500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3664823 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3664823 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420260 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.420260 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162883 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162883 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.216250 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.216319 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.216250 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.216319 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60509.975062 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60509.975062 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.002550 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.002550 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60500.005580 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60500.005580 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1032614 # number of writebacks
system.cpu.l2cache.writebacks::total 1032614 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 794006 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 794006 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176407 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176407 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1970413 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1971215 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1970413 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1971215 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40097303000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40097303000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40509000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40509000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59408556500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59408556500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40509000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99505859500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 99546368500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40509000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99505859500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 99546368500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420260 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420260 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162883 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162883 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216319 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1938767 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1177209 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution
system.membus.trans_dist::CleanEvict 905103 # Transaction distribution
system.membus.trans_dist::ReadExReq 794006 # Transaction distribution
system.membus.trans_dist::ReadExResp 794006 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1971215 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1971215 # Request fanout histogram
system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------

877
tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
View file

@ -1,877 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
View file

@ -1,7 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

29
tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
View file

@ -1,29 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:43
gem5 executing on e108600-lin, pid 28042
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 53437621500 because target called exit()

795
tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,795 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.053438 # Number of seconds simulated
sim_ticks 53437621500 # Number of ticks simulated
final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 468238 # Simulator instruction rate (inst/s)
host_op_rate 468238 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 272260061 # Simulator tick rate (ticks/s)
host_mem_usage 257916 # Number of bytes of host memory used
host_seconds 196.27 # Real time elapsed on the host
sim_insts 91903089 # Number of instructions simulated
sim_ops 91903089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory
system.physmem.bytes_read::total 340608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 202880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 202880 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5322 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 340608 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 340608 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 468 # Per bank write bursts
system.physmem.perBankRdBursts::1 295 # Per bank write bursts
system.physmem.perBankRdBursts::2 308 # Per bank write bursts
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
system.physmem.perBankRdBursts::4 224 # Per bank write bursts
system.physmem.perBankRdBursts::5 238 # Per bank write bursts
system.physmem.perBankRdBursts::6 222 # Per bank write bursts
system.physmem.perBankRdBursts::7 289 # Per bank write bursts
system.physmem.perBankRdBursts::8 254 # Per bank write bursts
system.physmem.perBankRdBursts::9 282 # Per bank write bursts
system.physmem.perBankRdBursts::10 254 # Per bank write bursts
system.physmem.perBankRdBursts::11 261 # Per bank write bursts
system.physmem.perBankRdBursts::12 410 # Per bank write bursts
system.physmem.perBankRdBursts::13 344 # Per bank write bursts
system.physmem.perBankRdBursts::14 501 # Per bank write bursts
system.physmem.perBankRdBursts::15 448 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 53437285500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 5322 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation
system.physmem.totQLat 132267250 # Total ticks spent queuing
system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers
system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4338 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 10040827.79 # Average gap between requests
system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ)
system.physmem_0.averagePower 250.626273 # Core power per rank (mW)
system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states
system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states
system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states
system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ)
system.physmem_1.averagePower 251.716611 # Core power per rank (mW)
system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states
system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states
system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 11450652 # Number of BP lookups
system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 2073 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20415218 # DTB read hits
system.cpu.dtb.read_misses 43383 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20458601 # DTB read accesses
system.cpu.dtb.write_hits 6579912 # DTB write hits
system.cpu.dtb.write_misses 276 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6580188 # DTB write accesses
system.cpu.dtb.data_hits 26995130 # DTB hits
system.cpu.dtb.data_misses 43659 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 27038789 # DTB accesses
system.cpu.itb.fetch_hits 22968644 # ITB hits
system.cpu.itb.fetch_misses 90 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 22968734 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 106875243 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903089 # Number of instructions committed
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.162912 # CPI: cycles per instruction
system.cpu.ipc 0.859910 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::MemRead 19433628 21.15% 92.31% # Class of committed instruction
system.cpu.op_class_0::MemWrite 6424338 6.99% 99.30% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 76788 0.08% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91903089 # Class of committed instruction
system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits
system.cpu.dcache.overall_hits::total 26572187 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses
system.cpu.dcache.overall_misses::total 3415 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1743 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2231 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 13865 # number of replacements
system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses
system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits
system.cpu.icache.overall_hits::total 22952813 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses
system.cpu.icache.overall_misses::total 15831 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 456439000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 456439000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 456439000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 456439000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 456439000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 456439000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22968644 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22968644 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22968644 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22968644 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22968644 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22968644 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 13865 # number of writebacks
system.cpu.icache.writebacks::total 13865 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15831 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15831 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15831 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13865 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12660 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 12660 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12660 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 12739 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12660 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 12739 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1717 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1717 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3170 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3170 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 435 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 435 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2152 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5322 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses
system.cpu.l2cache.overall_misses::total 5322 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 13865 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1743 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1743 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15830 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15830 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 488 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 488 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15830 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2231 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 18061 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15830 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2231 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 18061 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985083 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985083 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200253 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200253 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.891393 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.891393 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200253 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964590 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.294668 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1717 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1717 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3170 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3170 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 435 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 435 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2152 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5322 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200253 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.891393 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.891393 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1743 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1743 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15830 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 488 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45525 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4619 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 50144 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1900480 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2050112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 18061 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 18061 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 18061 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 30013500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23745000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3605 # Transaction distribution
system.membus.trans_dist::ReadExReq 1717 # Transaction distribution
system.membus.trans_dist::ReadExResp 1717 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3605 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10644 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10644 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 340608 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 5322 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 5322 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5322 # Request fanout histogram
system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

825
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,825 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

7
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,7 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

29
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -1,29 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 28064
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 21954917500 because target called exit()

276
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
View file

@ -1,276 +0,0 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
View file

@ -1,17 +0,0 @@
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
View file

@ -1,11 +0,0 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
View file

@ -1,2 +0,0 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
View file

@ -1,18 +0,0 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
View file

@ -1,19 +0,0 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
View file

@ -1,29 +0,0 @@
net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

1074
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

877
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
View file

@ -1,877 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

4
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr
View file

@ -1,4 +0,0 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ignoring syscall sigprocmask(1, ...)

15
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
View file

@ -1,15 +0,0 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 28071
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 22083000 because target called exit()

Some files were not shown because too many files have changed in this diff Show more