gem5/arch/alpha
Kevin Lim 70b35bab57 Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
2006-02-27 11:44:35 -05:00
..
isa Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. 2006-02-27 11:44:35 -05:00
alpha_linux_process.cc Add pipe() syscall to Alpha Linux emulation. 2006-02-23 08:16:59 -05:00
alpha_linux_process.hh Move Linux/Tru64 architecture independent code into kern/* 2006-02-18 23:44:22 -05:00
alpha_memory.cc Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. 2006-02-27 11:44:35 -05:00
alpha_memory.hh Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. 2006-02-21 20:10:40 -05:00
alpha_tru64_process.cc Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 2006-02-19 03:20:05 -05:00
alpha_tru64_process.hh Move Linux/Tru64 architecture independent code into kern/* 2006-02-18 23:44:22 -05:00
aout_machdep.h Many files: 2005-06-05 05:16:00 -04:00
arguments.cc Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
arguments.hh Many files: 2005-06-05 05:16:00 -04:00
ecoff_machdep.h Many files: 2005-06-05 04:21:22 -04:00
ev5.cc Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. 2006-02-27 11:44:35 -05:00
ev5.hh Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
faults.cc Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. 2006-02-21 20:10:40 -05:00
faults.hh Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. 2006-02-21 20:10:40 -05:00
isa_traits.hh Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. 2006-02-27 11:44:35 -05:00
osfpal.cc Many files: 2005-06-05 05:16:00 -04:00
osfpal.hh Many files: 2005-06-05 05:16:00 -04:00
SConscript Create a Builder object for .isa files in arch/SConscript. 2006-02-23 14:31:15 -05:00
stacktrace.cc Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. 2006-02-27 11:44:35 -05:00
stacktrace.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
vtophys.cc Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. 2006-02-27 11:44:35 -05:00
vtophys.hh Made Addr a global type 2006-02-21 03:38:21 -05:00