6c72c35519
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which distinguishes writes to the INT and FP register banks. Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72, where the "latency" of FMADD is 3 if the next instruction is a FMADD and has only the augend to destination dependency, otherwise it's 7 cycles. Signed-off-by: Jason Lowe-Power <jason@lowepower.com> |
||
---|---|---|
.. | ||
alpha | ||
arm | ||
generic | ||
hsail | ||
mips | ||
null | ||
power | ||
sparc | ||
x86 | ||
isa_parser.py | ||
micro_asm.py | ||
micro_asm_test.py | ||
SConscript |