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hsail: Fix disassembly of load instruction with 3 destination operands

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This commit is contained in:
Alexandru Dutu 2016-09-16 12:36:20 -04:00
parent bd65ec0744
commit 68127ca3da
1 changed files with 9 additions and 0 deletions
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9
src/arch/hsail/insts/mem_impl.hh
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@ -93,6 +93,15 @@ namespace HsailISA
this->dest_vect[1].disassemble(),
this->addr.disassemble());
break;
case 3:
this->disassembly = csprintf("%s_%s_%s (%s,%s,%s), %s", this->opcode,
segmentNames[this->segment],
MemDataType::label,
this->dest_vect[0].disassemble(),
this->dest_vect[1].disassemble(),
this->dest_vect[2].disassemble(),
this->addr.disassemble());
break;
case 4:
this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s",
this->opcode,