From 68127ca3da543db0c2f3d131d2b3f3525a35ec50 Mon Sep 17 00:00:00 2001 From: Alexandru Dutu Date: Fri, 16 Sep 2016 12:36:20 -0400 Subject: [PATCH] hsail: Fix disassembly of load instruction with 3 destination operands --- src/arch/hsail/insts/mem_impl.hh | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/arch/hsail/insts/mem_impl.hh b/src/arch/hsail/insts/mem_impl.hh index 3042e2201..e3529f914 100644 --- a/src/arch/hsail/insts/mem_impl.hh +++ b/src/arch/hsail/insts/mem_impl.hh @@ -93,6 +93,15 @@ namespace HsailISA this->dest_vect[1].disassemble(), this->addr.disassemble()); break; + case 3: + this->disassembly = csprintf("%s_%s_%s (%s,%s,%s), %s", this->opcode, + segmentNames[this->segment], + MemDataType::label, + this->dest_vect[0].disassemble(), + this->dest_vect[1].disassemble(), + this->dest_vect[2].disassemble(), + this->addr.disassemble()); + break; case 4: this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s", this->opcode,