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gem5/src/arch/arm
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Ali Saidi 649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes. 
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
..
insts StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
isa ARM: Add support for DIV/SDIV instructions. 2011-08-19 15:08:07 -05:00
linux ARM: Mark some variables uncacheable until boot all CPUs are enabled. 2011-08-19 15:08:08 -05:00
ArmInterrupts.py ARM: Boilerplate full-system code. 2009-11-17 18:02:08 -06:00
ArmNativeTrace.py ARM: Make the ARM native tracer stop M5 if control diverges. 2009-07-29 00:17:11 -07:00
ArmSystem.py ARM: Add VExpress_E support with PCIe to gem5 2011-08-19 15:08:08 -05:00
ArmTLB.py ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. 2010-06-02 12:58:16 -05:00
faults.cc LSQ: Only trigger a memory violation with a load/load if the value changes. 2011-09-13 12:58:08 -04:00
faults.hh LSQ: Only trigger a memory violation with a load/load if the value changes. 2011-09-13 12:58:08 -04:00
interrupts.cc ARM: Implement ARM CPU interrupts 2010-06-02 12:58:16 -05:00
interrupts.hh Fix bugs due to interaction between SEV instructions and O3 pipeline 2011-08-19 15:08:07 -05:00
intregs.hh ARM: Further break up condition code into NZ, C, V bits. 2011-05-13 17:27:01 -05:00
isa.cc ARM: Mark some variables uncacheable until boot all CPUs are enabled. 2011-08-19 15:08:08 -05:00
isa.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
isa_traits.hh StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
kernel_stats.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
locked_mem.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
microcode_rom.hh arm: include missing file for arm 2009-04-21 15:40:26 -07:00
miscregs.cc ARM: Adds dummy support for a L2 latency miscreg. 2011-02-23 15:10:48 -06:00
miscregs.hh ARM: Add two unimplemented miscellaneous registers. 2011-07-15 11:53:34 -05:00
mmapped_ipr.hh Spelling: Fix the a spelling error by changing mmaped to mmapped. 2011-03-01 23:18:47 -08:00
nativetrace.cc ARM: Further break up condition code into NZ, C, V bits. 2011-05-13 17:27:01 -05:00
nativetrace.hh ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
pagetable.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
predecoder.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
predecoder.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
process.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
process.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
registers.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
remote_gdb.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
remote_gdb.hh ARM: Add support for GDB on ARM 2010-11-15 14:04:03 -06:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
SConsopts arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
stacktrace.cc sim: Use forward declarations for ports. 2010-11-08 13:58:22 -06:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
system.cc ARM: Better RealView/Versatile EB platform support. 2011-05-13 17:27:00 -05:00
system.hh ARM: Mark some variables uncacheable until boot all CPUs are enabled. 2011-08-19 15:08:08 -05:00
table_walker.cc ARM: Fix a memory leak with the table walker. 2011-08-19 15:08:05 -05:00
table_walker.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
tlb.cc ARM: Mark some variables uncacheable until boot all CPUs are enabled. 2011-08-19 15:08:08 -05:00
tlb.hh ARM: Mark some variables uncacheable until boot all CPUs are enabled. 2011-08-19 15:08:08 -05:00
types.hh cpus/isa: add a != operator for pcstate 2011-06-19 21:43:33 -04:00
utility.cc ARM: Add support for loading the a bootloader and configuring parameters for it 2011-05-04 20:38:28 -05:00
utility.hh ARM: Further break up condition code into NZ, C, V bits. 2011-05-13 17:27:01 -05:00
vtophys.cc ARM: Implement functional virtual to physical address translation 2010-10-01 16:03:27 -05:00
vtophys.hh includes: sort all includes 2011-04-15 10:44:06 -07:00