Andreas Sandberg abe7ef95cb sim: Remove redundant export_method_cxx_predecls ... The headers declared in export_method_cxx_predecls are redundant since a SimObject's main header is automatically included. Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Joe Gross <joseph.gross@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>		2017-01-03 12:03:06 +00:00
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alpha	alpha: Remove ALPHA tru64 support and associated tests	2016-11-17 04:54:14 -05:00
arm	sim: Remove redundant export_method_cxx_predecls	2017-01-03 12:03:06 +00:00
generic	cpu, arch: fix the type used for the request flags	2016-08-15 12:00:35 +01:00
hsail	hsail: disable asserts to allow immediate operands i.e. 0 with loads	2016-12-02 18:01:58 -05:00
mips	isa: Modify get/check interrupt routines	2016-07-21 17:19:15 +01:00
null	cpu,isa,mem: Add per-thread wakeup logic	2015-09-30 11:14:19 -05:00
power	isa: Modify get/check interrupt routines	2016-07-21 17:19:15 +01:00
riscv	riscv: [Patch 7/5] Corrected LRSC semantics	2016-11-30 17:10:28 -05:00
sparc	isa: Modify get/check interrupt routines	2016-07-21 17:19:15 +01:00
x86	syscall_emul: implement fallocate	2016-12-15 13:16:25 -05:00
isa_parser.py	cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass	2016-10-15 14:58:45 -05:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF	2016-10-26 22:47:38 -04:00