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Andreas Hansson 5a9a743cfc MEM: Introduce the master/slave port roles in the Python classes 
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
..
alpha MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
arm MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
mips SE/FS: Get rid of FULL_SYSTEM in MIPS. 2011-10-30 18:39:38 -07:00
sparc Merge with the main repo. 2012-01-28 07:24:01 -08:00
x86 MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
baddev.cc SE/FS: Put platform pointers in fewer objects. 2011-10-04 02:26:03 -07:00
baddev.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
BadDevice.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
copy_engine.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
copy_engine.hh MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
copy_engine_defs.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
CopyEngine.py CopyEngine: Implement a I/OAT-like copy engine. 2009-01-17 18:55:09 -05:00
Device.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
disk_image.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
disk_image.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
DiskImage.py Config: Cause a fatal() when a parameter without a default value isn't set(FS #315). 2009-01-30 19:08:13 -05:00
etherbus.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
etherbus.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
etherdevice.cc stats: only consider a formula initialized if there is a formula 2010-06-15 01:18:36 -07:00
etherdevice.hh stats: Fix all stats usages to deal with template fixes 2009-03-05 19:09:53 -08:00
etherdump.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
etherdump.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
etherint.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
etherint.hh Devices: Make EtherInts connect in the same way memory ports currently do. 2007-08-16 16:49:02 -04:00
etherlink.cc event: minor cleanup 2011-09-22 18:59:55 -07:00
etherlink.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
Ethernet.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
etherobject.hh Devices: Make EtherInts connect in the same way memory ports currently do. 2007-08-16 16:49:02 -04:00
etherpkt.cc PacketFifo: Get slack out of the EthPacketData structure. This allows 2008-06-17 21:34:27 -07:00
etherpkt.hh types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
ethertap.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
ethertap.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
i8254xGBe.cc gcc: fix unused variable warnings from GCC 4.6.1 2011-12-13 11:49:27 -08:00
i8254xGBe.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
i8254xGBe_defs.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
Ide.py ARM: Add support for a dumb IDE controller 2010-11-15 14:04:03 -06:00
ide_atareg.h make our code a little more standards compliant 2007-01-26 18:48:51 -05:00
ide_ctrl.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
ide_ctrl.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
ide_disk.cc IDE: Fix issues with new PIIX kernel driver and our model. 2011-08-19 15:08:08 -05:00
ide_disk.hh IDE: Fix issues with new PIIX kernel driver and our model. 2011-08-19 15:08:08 -05:00
ide_wdcreg.h copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
intel_8254_timer.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
intel_8254_timer.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
io_device.cc mem: Add a master ID to each request object. 2012-02-12 16:07:38 -06:00
io_device.hh mem: Add a master ID to each request object. 2012-02-12 16:07:38 -06:00
isa_fake.cc IO: Handle case where ISA Fake device is being used as a fake memory. 2011-07-10 12:56:08 -05:00
isa_fake.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
mc146818.cc mc146818: Correctly serialize tickEvent 2011-10-10 17:01:33 -05:00
mc146818.hh Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
ns_gige.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
ns_gige.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
ns_gige_reg.h X86: Get X86_FS to compile. 2007-09-24 17:39:56 -07:00
Pci.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
pciconfigall.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
pciconfigall.hh MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
pcidev.cc Merge with head, hopefully the last time for this batch. 2012-01-31 22:40:08 -08:00
pcidev.hh Merge with the main repo. 2012-01-28 07:24:01 -08:00
pcireg.h style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
pktfifo.cc types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
pktfifo.hh types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
platform.cc Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed. 2011-02-23 15:10:49 -06:00
platform.hh SE/FS: Remove System::platform and Platform::intrFrequency. 2011-09-30 00:29:07 -07:00
Platform.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
ps2.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
ps2.hh VNC/ARM: Use VNC server and add support to boot into X11 2011-02-11 18:29:36 -06:00
rtcreg.h X86: Turn #defines into consts. 2008-03-25 02:09:18 -04:00
SConscript SE/FS: Build the devices in SE mode. 2011-09-30 00:28:33 -07:00
simple_disk.cc MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
simple_disk.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
SimpleDisk.py Fix miscellaneous small typos. 2007-08-30 15:16:59 -04:00
sinic.cc MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
sinic.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
sinicreg.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
terminal.cc gcc: fix unused variable warnings from GCC 4.6.1 2011-12-13 11:49:27 -08:00
terminal.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
Terminal.py Change the default output filename for the terminal so it's more obvious. 2008-06-17 20:30:37 -07:00
uart.cc Rename SimConsole to Terminal since it makes more sense 2008-06-17 20:29:06 -07:00
uart.hh Rename SimConsole to Terminal since it makes more sense 2008-06-17 20:29:06 -07:00
Uart.py SE/FS: Put platform pointers in fewer objects. 2011-10-04 02:26:03 -07:00
uart8250.cc MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
uart8250.hh MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00