Andreas Hansson 54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width ... This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.		2012-10-15 08:09:54 -04:00
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tsunami-simple-atomic	Stats: Update stats for use of two-level builder	2012-10-15 08:08:06 -04:00
tsunami-simple-atomic-dual	stats: update stats for icache change not allowing dirty data	2012-07-27 16:08:05 -04:00
tsunami-simple-timing	Stats: Update stats for new default L1-to-L2 bus clock and width	2012-10-15 08:09:54 -04:00
tsunami-simple-timing-dual	Stats: Update stats to reflect SimpleMemory bandwidth	2012-09-18 10:30:04 -04:00