c27c122afc
change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9 |
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.. | ||
AlphaConsole.py | ||
AlphaFullCPU.py | ||
AlphaTLB.py | ||
BadDevice.py | ||
BaseCache.py | ||
BaseCPU.py | ||
Bus.py | ||
CoherenceProtocol.py | ||
Device.py | ||
DiskImage.py | ||
Ethernet.py | ||
Ide.py | ||
IntrControl.py | ||
MemObject.py | ||
MemTest.py | ||
Pci.py | ||
PhysicalMemory.py | ||
Platform.py | ||
Process.py | ||
Repl.py | ||
Root.py | ||
SimConsole.py | ||
SimpleDisk.py | ||
System.py | ||
Tsunami.py | ||
Uart.py |