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gem5/src/sim
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Andreas Sandberg 38925ff621 arm: Remove the register mapping hack used when copying TCs 
In order to see all registers independent of the current CPU mode, the
ARM architecture model uses the magic MISCREG_CPSR_MODE register to
change the register mappings without actually updating the CPU
mode. This hack is no longer needed since the thread context now
provides a flat interface to the register file. This patch replaces
the CPSR_MODE hack with the flat register interface.
2013-01-07 13:05:44 -05:00
..
arguments.cc GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
arguments.hh gcc: Small fixes to compile with gcc 4.7 2012-05-30 05:31:48 -04:00
async.cc Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
async.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
BaseTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
byteswap.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
clocked_object.hh sim: Fatal if a clocked object is set to have a clock of 0 2013-01-07 13:05:39 -05:00
ClockedObject.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
core.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
core.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
debug.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
debug.hh Debug: Add a function to cause the simulator to create a checkpoint from GDB. 2011-05-04 20:38:27 -05:00
drain.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
drain.hh sim: Add drain methods to request additional cleanup operations 2012-11-02 11:32:02 -05:00
eventq.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
eventq.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
eventq_impl.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
fault_fwd.hh copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
faults.cc SE/FS: Get rid of FULL_SYSTEM in sim. 2011-11-02 02:11:14 -07:00
faults.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
full_system.hh clang: Fix recently introduced clang compilation errors 2012-03-19 06:35:04 -04:00
init.cc base: Add wrapped protobuf output streams 2013-01-07 13:05:37 -05:00
init.hh clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 2012-04-14 05:43:31 -04:00
insttracer.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
InstTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
main.cc libm5: Create a libm5 static library for embedding m5. 2008-08-03 18:19:54 -07:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
process.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
process.hh process: add progName() virtual function 2012-08-06 16:55:34 -07:00
Process.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
process_impl.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
pseudo_inst.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
pseudo_inst.hh Merge with head, hopefully the last time for this batch. 2012-01-31 22:40:08 -08:00
root.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
root.hh sim: Provide a framework for detecting out of data checkpoints and migrating them. 2012-06-05 01:23:10 -04:00
Root.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
SConscript sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
serialize.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
serialize.hh arm: Remove the register mapping hack used when copying TCs 2013-01-07 13:05:44 -05:00
sim_events.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
sim_events.hh sim: clean up CountedDrainEvent slightly. 2011-01-07 21:50:29 -08:00
sim_exit.hh Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
sim_object.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
sim_object.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
simulate.cc sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
simulate.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
stat_control.cc Statistics: Add a function to configure periodic stats dumping 2012-09-25 11:49:41 -05:00
stat_control.hh Statistics: Add a function to configure periodic stats dumping 2012-09-25 11:49:41 -05:00
stats.hh stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
syscall_emul.cc SPARC: Keep a copy of the current ASI in the decoder. 2013-01-04 18:09:45 -06:00
syscall_emul.hh SE: Ignore FUTEX_PRIVATE_FLAG of sys_futex 2012-09-21 04:51:18 -04:00
syscallreturn.hh includes: use base/types.hh not inttypes.h or stdint.h 2009-05-17 14:34:51 -07:00
system.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
system.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
System.py config: Do not use hardcoded physmem in fs script 2013-01-07 13:05:38 -05:00
tlb.cc SE/FS: Get rid of FULL_SYSTEM in sim. 2011-11-02 02:11:14 -07:00
tlb.hh arch: Add support for invalidating TLBs when draining 2013-01-07 13:05:40 -05:00
vptr.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00