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gem5/src/cpu
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Andreas Hansson 07cf9d914b MEM: Separate queries for snooping and address ranges 
This patch simplifies the address-range determination mechanism and
also unifies the naming across ports and devices. It further splits
the queries for determining if a port is snooping and what address
ranges it responds to (aiming towards a separation of
cache-maintenance ports and pure memory-mapped ports). Default
behaviours are such that most ports do not have to define isSnooping,
and master ports need not implement getAddrRanges.
2012-01-17 12:55:09 -06:00
..
checker MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
inorder MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
nocpu SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
o3 MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
ozone MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
pred O3: Fix uninitialized variable in the tournament branch predictor. 2011-08-07 09:21:49 -07:00
simple MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
testers MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
trace includes: sort all includes 2011-04-15 10:44:06 -07:00
activity.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
activity.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
base.cc MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
base.hh MEM: Separate queries for snooping and address ranges 2012-01-17 12:55:09 -06:00
base_dyn_inst.hh LSQ: Only trigger a memory violation with a load/load if the value changes. 2011-09-13 12:58:08 -04:00
base_dyn_inst_impl.hh LSQ: Only trigger a memory violation with a load/load if the value changes. 2011-09-13 12:58:08 -04:00
BaseCPU.py CPU: Moving towards a more general port across CPU models 2012-01-17 12:55:08 -06:00
CheckerCPU.py python: Move more code into m5.util allow SCons to use that code. 2009-09-22 15:24:16 -07:00
cpuevent.cc
cpuevent.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
decode.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
decode.hh Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
decode_cache.hh Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
exec_context.hh ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
exetrace.cc Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. 2011-05-13 17:27:00 -05:00
exetrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
ExeTracer.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
FuncUnit.py CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
inteltrace.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
inteltrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
IntelTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
intr_control.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
intr_control.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc GCC: Get everything working with gcc 4.6.1. 2011-10-31 01:09:44 -07:00
legiontrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
LegionTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
m5legion_interface.h
nativetrace.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
nativetrace.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
NativeTrace.py ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
op_class.hh CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
pc_event.cc CPU: Remove Alpha-specific PC alignment check. 2012-01-09 20:05:07 -05:00
pc_event.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
profile.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
profile.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
quiesce_event.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
quiesce_event.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
sched_list.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
SConscript Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
simple_thread.cc MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
simple_thread.hh MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
smt.hh includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
static_inst.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
static_inst.hh StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
static_inst_fwd.hh StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
thread_context.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
thread_context.hh MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
thread_state.cc MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
thread_state.hh MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
timebuf.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
translation.hh Translation: Use a pointer type as the template argument. 2011-08-07 09:21:48 -07:00