Nilay Vaish 63563c9df2 O3, Ruby: Forward invalidations from Ruby to O3 CPU ... This patch implements the functionality for forwarding invalidations and replacements from the L1 cache of the Ruby memory system to the O3 CPU. The implementation adds a list of ports to RubyPort. Whenever a replacement or an invalidation is performed, the L1 cache forwards this to all the ports, which is the LSQ in case of the O3 CPU.		2012-01-23 11:07:14 -06:00
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arch	MEM: Separate queries for snooping and address ranges	2012-01-17 12:55:09 -06:00
base	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
cpu	MEM: Separate queries for snooping and address ranges	2012-01-17 12:55:09 -06:00
dev	MEM: Removing the default port peer from Python ports	2012-01-17 12:55:09 -06:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	MEM: Separate queries for snooping and address ranges	2012-01-17 12:55:09 -06:00
mem	O3, Ruby: Forward invalidations from Ruby to O3 CPU	2012-01-23 11:07:14 -06:00
python	MEM: Removing the default port peer from Python ports	2012-01-17 12:55:09 -06:00
sim	MEM: Separate queries for snooping and address ranges	2012-01-17 12:55:09 -06:00
unittest	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	SWIG: Make gem5 compile and link with swig 2.0.4	2012-01-09 18:08:20 -06:00