Korey Sewell 19534176e0 load/store instruction format ... now generates load/store code ... and breaks it into a separate EA and MemAccess templated from how the Alpha ARch. was coded to do the same thing. arch/mips/isa/bitfields.isa: comment change arch/mips/isa/decoder.isa: re-structuring of load/store instruction definitions arch/mips/isa/formats/mem.isa: Define LoadMemory & Store Memory formats Use style of formatting & base class similar to what was used for ALPHA arch/mips/isa/formats/util.isa: Insert LoadStoreBase function here from alpha/arch/isa/mem.isa arch/mips/isa/operands.isa: change shw->sh and uhw->uh --HG-- extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a		2006-02-20 14:30:23 -05:00
..
formats	load/store instruction format ... now generates load/store code	2006-02-20 14:30:23 -05:00
base.isa	Support NNPC and branch instructions ... Outputs to decoder.cc correctly	2006-02-18 23:17:45 -05:00
bitfields.isa	load/store instruction format ... now generates load/store code	2006-02-20 14:30:23 -05:00
decoder.isa	load/store instruction format ... now generates load/store code	2006-02-20 14:30:23 -05:00
formats.isa	MIPS generates ISA code through scons '.../decoder.cc'!!!	2006-02-18 03:12:04 -05:00
includes.isa	name changes ... minor IntOP format change	2006-02-07 18:36:08 -05:00
main.isa	trying to get ISA to parse correctly ...	2006-02-14 21:26:01 -05:00
operands.isa	load/store instruction format ... now generates load/store code	2006-02-20 14:30:23 -05:00