a48c24b61e
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
63 lines
1.7 KiB
C++
63 lines
1.7 KiB
C++
// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Base class for MIPS instructions, and some support functions
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//
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//Outputs to decoder.hh
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output header {{
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/**
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* Base class for all SPARC static instructions.
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*/
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class MipsStaticInst : public StaticInst<MIPSISA>
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{
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protected:
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// Constructor.
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MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
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: StaticInst<MIPSISA>(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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//Ouputs to decoder.cc
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output decoder {{
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std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if(_numSrcRegs > 0)
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{
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printReg(ss, _srcRegIdx[0]);
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}
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if(_numSrcRegs > 1)
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{
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if(_numDestRegs > 0)
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{
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if(_numSrcRegs > 0)
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ss << ",";
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printReg(ss, _destRegIdx[0]);
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}
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return ss.str();
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}
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}};
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