19534176e0
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
54 lines
1.2 KiB
C++
54 lines
1.2 KiB
C++
// -*- mode:c++ -*-
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Bitfield definitions.
|
|
//
|
|
|
|
def bitfield OPCODE_HI <31:29>;
|
|
def bitfield OPCODE_LO <28:26>;
|
|
|
|
def bitfield FUNCTION_HI < 5: 3>;
|
|
def bitfield FUNCTION_LO < 2: 0>;
|
|
|
|
// Integer operate format
|
|
def bitfield RT <20:16>;
|
|
def bitfield RT_HI <20:19>;
|
|
def bitfield RT_LO <18:16>;
|
|
|
|
def bitfield RS <25:21>;
|
|
def bitfield RS_MSB <25:25>;
|
|
def bitfield RS_HI <25:24>;
|
|
def bitfield RS_LO <23:21>;
|
|
|
|
def bitfield RD <15:11>;
|
|
|
|
def bitfield INTIMM <15: 0>; // integer immediate (literal)
|
|
|
|
// Floating-point operate format
|
|
def bitfield FMT <25:21>;
|
|
def bitfield FT <20:16>;
|
|
def bitfield FS <15:11>;
|
|
def bitfield FD <10:6>;
|
|
|
|
def bitfield MOVCI <16:16>;
|
|
def bitfield MOVCF <16:16>;
|
|
def bitfield SRL <21:21>;
|
|
def bitfield SRLV < 6: 6>;
|
|
def bitfield SA <10: 6>;
|
|
|
|
// Interrupts
|
|
def bitfield SC < 5: 5>;
|
|
|
|
// Branch format
|
|
def bitfield OFFSET <15: 0>; // displacement
|
|
|
|
// Jmp format
|
|
def bitfield JMPTARG <25: 0>;
|
|
def bitfield JMPHINT <10: 6>;
|
|
|
|
def bitfield SYSCALLCODE <25: 6>;
|
|
def bitfield TRAPCODE <15:13>;
|
|
|
|
// M5 instructions
|
|
def bitfield M5FUNC <7:0>;
|