Alec Roelke 070da98493 riscv: [Patch 2/5] Added RISC-V multiply extension RV64M ... Second of five patches adding RISC-V to GEM5. This patch adds the RV64M extension, which includes integer multiply and divide instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I. Patch 3 will implement the floating point extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A; and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Added mulw instruction that was missed when dividing changes among patches.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>		2016-11-30 17:10:28 -05:00
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alpha	alpha: Remove ALPHA tru64 support and associated tests	2016-11-17 04:54:14 -05:00
arm	cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass	2016-10-15 14:58:45 -05:00
generic	cpu, arch: fix the type used for the request flags	2016-08-15 12:00:35 +01:00
hsail	hsail,gpu-compute: fixes to appease clang++	2016-10-26 22:48:45 -04:00
mips	isa: Modify get/check interrupt routines	2016-07-21 17:19:15 +01:00
null	cpu,isa,mem: Add per-thread wakeup logic	2015-09-30 11:14:19 -05:00
power	isa: Modify get/check interrupt routines	2016-07-21 17:19:15 +01:00
riscv	riscv: [Patch 2/5] Added RISC-V multiply extension RV64M	2016-11-30 17:10:28 -05:00
sparc	isa: Modify get/check interrupt routines	2016-07-21 17:19:15 +01:00
x86	x86: fix issue with casting in Cvtf2i	2016-11-21 15:35:56 -05:00
isa_parser.py	cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass	2016-10-15 14:58:45 -05:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF	2016-10-26 22:47:38 -04:00