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gem5/src/cpu
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Dam Sunwoo 81406018b0 ARM: dump stats and process info on context switches 
This patch enables dumping statistics and Linux process information on
context switch boundaries (__switch_to() calls) that are used for
Streamline integration (a graphical statistics viewer from ARM).
2012-11-02 11:32:01 -05:00
..
checker Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
inorder Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
nocpu SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
o3 O3: Pack the comm structures a bit better to reduce their size. 2012-09-25 11:49:40 -05:00
ozone CPU: Remove overloaded function_trace_start parameter 2012-08-21 05:49:43 -04:00
pred o3: Fix a couple of issues with the local predictor. 2012-11-02 11:32:00 -05:00
simple ARM: Squash outstanding walks when instructions are squashed. 2012-09-25 11:49:40 -05:00
testers memtest: move check on outstanding requests 2012-10-15 17:27:17 -05:00
trace includes: sort all includes 2011-04-15 10:44:06 -07:00
activity.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
activity.hh Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
base.cc ARM: dump stats and process info on context switches 2012-11-02 11:32:01 -05:00
base.hh ARM: dump stats and process info on context switches 2012-11-02 11:32:01 -05:00
base_dyn_inst.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
base_dyn_inst_impl.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
BaseCPU.py Regression: Use CPU clock and 32-byte width for L1-L2 bus 2012-10-15 08:08:08 -04:00
CheckerCPU.py CPU: Remove overloaded function_trace_start parameter 2012-08-21 05:49:43 -04:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
decode_cache.hh ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
dummy_checker_builder.cc CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable 2012-03-09 09:59:27 -05:00
DummyChecker.py CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 2012-01-31 07:46:03 -08:00
exec_context.hh SE/FS: Expose the same methods on the CPUs in SE and FS modes. 2011-11-01 04:01:13 -07:00
exetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
exetrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
ExeTracer.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
FuncUnit.py Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
inteltrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
inteltrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
IntelTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
intr_control.cc SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 2011-11-18 01:33:28 -08:00
intr_control.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc Fix: Address a few minor issues identified by cppcheck 2012-10-15 08:12:23 -04:00
legiontrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
LegionTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
nativetrace.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
NativeTrace.py ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
op_class.hh CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
pc_event.cc ARM: dump stats and process info on context switches 2012-11-02 11:32:01 -05:00
pc_event.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
profile.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
profile.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
quiesce_event.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
quiesce_event.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
SConscript ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
simple_thread.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
simple_thread.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
smt.hh includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
static_inst.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
static_inst.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
static_inst_fwd.hh StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
thread_context.cc SE/FS: Make the functions available from the TC consistent between SE and FS. 2011-10-31 02:58:22 -07:00
thread_context.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
thread_state.cc cpu: added assertions to ensure the correct proxies are used 2012-07-10 22:51:53 -07:00
thread_state.hh cpu: added assertions to ensure the correct proxies are used 2012-07-10 22:51:53 -07:00
timebuf.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
translation.hh ARM: Squash outstanding walks when instructions are squashed. 2012-09-25 11:49:40 -05:00