Commit graph

8923 commits

Author SHA1 Message Date
William Wang f9d403a7b9 MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 09:40:11 -04:00
Andreas Hansson a14013af3a CPU: Unify initMemProxies across CPUs and simulation modes
This patch unifies where initMemProxies is called, in the init()
method of each BaseCPU subclass, before TheISA::initCPU is
called. Moreover, it also ensures that initMemProxies is called in
both full-system and syscall-emulation mode, thus unifying also across
the modes. An additional check is added in the ThreadState to ensure
that initMemProxies is only called once.
2012-03-30 09:38:35 -04:00
Nilay Vaish 390cfc7be9 Config: Change the way options are added
I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.
2012-03-28 11:01:53 -05:00
Nilay Vaish 6ca3af8ecf Config: Move setWorkCountOptions() to Simulation.py
The function is presently defined in FSConfig.py, which does not seem to be
the correct place for it.
2012-03-27 18:23:21 -05:00
Andreas Hansson 9d7c715c46 range_map: Enable const find and iteration
This patch adds const access functions to the range_map to enable its use
in a const context, similar to the STL container classes.
2012-03-26 05:37:00 -04:00
Andreas Hansson 312efd742e Power: Change bitfield name to avoid conflicts with range_map
This patch changes the name of a bitfield from W to W_FIELD to avoid
clashes with W being used as a class (typename) in the templatized
range_map. It also changes L to L_FIELD to avoid future problems. The
problem manifestes itself when the CPU includes a header that in turn
includes range_map.hh. The relevant parts of the decoder are updated.
2012-03-26 05:35:24 -04:00
Andreas Hansson ca9790a2db Ruby: Fix Set::print for 32-bit hosts
This patch fixes a compilation error caused by a length mismatch on
32-bit hosts. The ifdef and sprintf is replaced by a csprintf.
2012-03-23 06:54:25 -04:00
Andreas Hansson 9727b1be18 MEM: Unify bus access methods and prepare for master/slave split
This patch unifies the recvFunctional, recvAtomic and recvTiming to
all be based on a similar structure: 1) extract information about the
incoming packet, 2) send it out to the appropriate snoopers, 3)
determine where it is going, and 4) forward it to the right
destination. The naming of variables across the different access
functions is now consistent as well.

Additionally, the patch introduces the member functions releaseBus and
retryWaiting to better distinguish between the two cases when we
should tell a sender to retry. The first case is when the bus goes
from busy to idle, and the second case is when it receives a retry
from a destination that did not immediatelly accept a packet.

As a very minor change, the MMU debug flag is no longer used in the bus.
2012-03-22 06:37:21 -04:00
Andreas Hansson c2d2ea99e3 MEM: Split SimpleTimingPort into PacketQueue and ports
This patch decouples the queueing and the port interactions to
simplify the introduction of the master and slave ports. By separating
the queueing functionality from the port itself, it becomes much
easier to distinguish between master and slave ports, and still retain
the queueing ability for both (without code duplication).

As part of the split into a PacketQueue and a port, there is now also
a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The
QueuedPort is useful for ports that want to leave the packet
transmission of outgoing packets to the queue and is used by both
master and slave ports. The SimpleTimingPort inherits from the
QueuedPort and adds the implemention of recvTiming and recvFunctional
through recvAtomic.

The PioPort and MessagePort are cleaned up as part of the changes.

--HG--
rename : src/mem/tport.cc => src/mem/packet_queue.cc
rename : src/mem/tport.hh => src/mem/packet_queue.hh
2012-03-22 06:36:27 -04:00
Andreas Hansson fb395b56dd Scons: Remove Werror=False in SConscript files
This patch removes the overriding of "-Werror" in a handful of
cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
warnings, and thus without any errors. There are no functional changes
introduced by this patch. In the future, rather than ypassing
"-Werror", address the warnings.
2012-03-22 06:34:50 -04:00
Andreas Hansson 12742835bc Python: Fix a conditional expression that requires Python 2.5
This patch changes a conditional expression to a conventional if/else
block, which does not require Python >= 2.5.
2012-03-21 19:02:03 -04:00
Ali Saidi 3c666083c6 ARM: Update stats for IT and conditional branch changes 2012-03-21 10:36:45 -05:00
Nathanael Premillieu 8e2a8fbb7e ARM: Fix case where cond/uncond control is mis-specified 2012-03-21 10:34:06 -05:00
Ali Saidi ed8ed6e761 ARM: Clean up condCodes in IT blocks. 2012-03-21 10:34:06 -05:00
Geoffrey Blake a64319f764 ARM: IT doesn't need to be serializing. 2012-03-21 10:34:06 -05:00
Andrew Lukefahr b4e5be717d O3: Fix sizing of decode to rename skid buffer. 2012-03-21 10:34:06 -05:00
Koan-Sin Tan 0376422c0b ARM: Add RTC to PBX System 2012-03-21 10:34:05 -05:00
Brian Grayson 565c1de4a8 O3: Fix size of skid buffer between fetch and decode when widths are different 2012-03-21 10:34:05 -05:00
Ali Saidi 1981ba21ca ARM: Fix uninitialized value in ARM RTC model. 2012-03-21 10:34:05 -05:00
Tushar Krishna c9e4bca8d8 Garnet: Stats at vnet granularity + code cleanup
This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.
2012-03-19 17:34:17 -04:00
Andreas Hansson 72538294fb gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
2012-03-19 06:36:09 -04:00
Andreas Hansson adb8621031 clang: Fix recently introduced clang compilation errors
This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.
2012-03-19 06:35:04 -04:00
Andreas Hansson a444a6f8d6 scripts: Fix to ensure that port connection count is always set
This patch ensures that the port connection count is set to zero in those
cases when the port is not connected.
2012-03-19 06:34:02 -04:00
Nilay Vaish f02eec93d6 ruby_fs.py: Add call to createInterruptController() 2012-03-16 07:47:03 -05:00
Nilay Vaish 13a5e9b7b5 FSConfig.py: fix a typo makeLinuxAlphaRubySystem 2012-03-16 07:46:45 -05:00
Marc Orr 24fe7cdf00 build: remove implicit-cache setting of scons from recent build faster patch 2012-03-16 03:29:07 -07:00
Nilay Vaish bb7be54d73 se.py: Changes to ruby portion due to SE/FS merge
With the SE/FS merge, interrupt controller is created irrespective of the
mode. This patch creates the interrupt controller when Ruby is used and
connects its ports.
2012-03-11 16:51:38 -05:00
Brian Grayson 98185658c5 O3: Add fatal when fetchWidth > Impl::MaxWidth. 2012-03-11 10:20:54 -04:00
Ali Saidi d2a0db7fe9 ARM: Fix memory starting at non-zero address and exceeding max mem for a system. 2012-03-09 16:45:47 -05:00
Ali Saidi 470051345a ARM: Update stats for CBNZ fix. 2012-03-09 15:33:07 -05:00
Brian Grayson 9a9a4a0780 ARM: Fix branch prediction issue with CB(N)Z instruction 2012-03-09 15:32:41 -05:00
Ali Saidi 927bba9d60 ARM: Update stats for valgrind fix and replace config.inis which are out of date. 2012-03-09 09:59:29 -05:00
Geoffrey Blake 69d229ce28 O3/Ozone: Eliminate dead code counting software prefetch insts
Eliminates dead code in the O3 and Ozone CPU models that counted
software prefetch instructions separately for the ALPHA ISA only.
2012-03-09 09:59:28 -05:00
Geoffrey Blake da0d67c3d6 CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
2012-03-09 09:59:28 -05:00
Geoffrey Blake 98cf57fb89 CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM.  This patch adds the appropriate function
stubs to allow compilation.
2012-03-09 09:59:28 -05:00
Geoffrey Blake 043709fdfa CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.
2012-03-09 09:59:27 -05:00
Ali Saidi df05ffab12 ARM: Don't reset CPUs that are going to be switched in. 2012-03-09 09:59:26 -05:00
Ali Saidi 3ce2d0fad0 System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into
initState(). This is needed for code that loads data into memory, however
for code that setups symbol tables, kernel based events, etc this is the wrong
thing to do as that code is only called when a checkpoint isn't being restored
from.
2012-03-09 09:59:26 -05:00
Ali Saidi ec1ef24895 ARM: Fix valgrind reported error on O3 that was causing minor stats changes. 2012-03-09 09:59:26 -05:00
Ali Saidi eaa994e7f6 cache: Allow main memory to be at disjoint address ranges. 2012-03-09 09:59:25 -05:00
Gabe Black cda4c2d280 Fix the SPARC fs regression by adding a call to createInterruptController. 2012-03-08 02:10:03 -08:00
Marc Orr eb43883bef build scripts: Made minor modifications to reduce build overhead time.
1. --implicit-cache behavior is default.
2. makeEnv in src/SConscript is conditionally called.
3. decider set to MD5-timestamp
4. NO_HTML build option changed to SLICC_HTML (defaults to False)
2012-03-06 19:07:41 -08:00
Andreas Hansson 75681d3c1b Stats: Update stats for changeset 8868
Changeset 8868 slightly changes the statistics for the parser and
bzip2 regressions for ARM o3-timing. This patch merely updates the
statistics to reflect these changes.
2012-03-06 11:14:54 -05:00
Steve Reinhardt 3418ebb5f8 SConstruct: rename and document AddM5Option
Got rid of gratuitous M5 reference in the function name.
In the process, wondered why we have this function at all and
spent time trying to get rid of it and eventually firgured out
why it's needed.  Put the answer in a comment so we don't have
to wonder again.
2012-03-02 14:05:00 -08:00
Steve Reinhardt f71a5c5e62 SConstruct: update comments & doc strings
Lots of references to 'M5' still, and some to SE/FS
2012-03-02 13:53:52 -08:00
Steve Reinhardt fd2d5ae2af DynInst: get rid of dead MyHash code.
Not sure what this was ever used for, but it
doesn't seem used anymore.
2012-03-02 09:17:42 -08:00
Andreas Hansson 32eae8094d CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.

The patch also adds the "createInterruptController" call to a number
of the regression scripts.
2012-03-02 09:21:48 -05:00
Andreas Hansson c0b9f324bf Stats: Fix the realview regression stats after nvmem move
This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.
2012-03-02 09:18:50 -05:00
Andreas Hansson adc419a13a Ruby: Rename RubyPort::sendTiming to avoid overriding base class
This patch renames the sendTiming member function in the RubyPort to
avoid inadvertently hiding Port::sendTiming (discovered through some
rather painful debugging). The RubyPort does, in fact, rely on the
functionality of the queued port and the implementation merely
schedules a send the next cycle. The new name for the member function
is sendNextCycle to better reflect this behaviour.

In the unlikely event that we ever shift to using C++11 the member
functions in Port should have a "final" identifier to prevent any
overriding in derived classes.
2012-03-02 09:16:50 -05:00
Ali Saidi b129d7ce00 ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available
before booting secondary CPUs.
2012-03-02 08:18:19 -06:00