Commit graph

257 commits

Author SHA1 Message Date
Steve Reinhardt
6b37bb6710 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
2007-02-07 10:55:14 -08:00
Steve Reinhardt
997fc505a8 Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.

--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-07 10:53:37 -08:00
Steve Reinhardt
23d970e6b9 More DPRINTF cleanup.
--HG--
extra : convert_revision : db89cea42b46476d19333038522a6c144eafdab1
2007-02-06 23:53:48 -08:00
Nathan Binkert
38db47005c Include compiler.hh since we use some of the #defines
--HG--
extra : convert_revision : 1040addcf3f52d8d9fed2930890dadf524205af9
2007-02-06 22:31:15 -08:00
Steve Reinhardt
51e54f519d Minor DPRINTF fixes.
--HG--
extra : convert_revision : 41956c9a480163ecac7807982215027e8ff1a4a9
2007-02-06 21:53:05 -08:00
Kevin Lim
310d8f0992 Fix for LL/SC that Ron sent me.
--HG--
extra : convert_revision : b3510a23d8a9eb466939f38491a109c3a65a7363
2007-02-06 15:54:44 -05:00
Ali Saidi
02bd40d552 While I'm waiting for legion to run make m5 compile with a few more compilers
SConstruct:
src/SConscript:
    Add flags for Intel CC while i'm at it
src/base/compiler.hh:
    the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way
src/base/cprintf_formats.hh:
    add std:: where appropriate
src/base/statistics.hh:
    use this->map since icc was getting confused about std::map vs the locally defined map
src/cpu/static_inst.hh:
    Add some more dummy returns where needed
src/mem/packet.hh:
    add more dummy returns where needed
src/sim/host.hh:
    use limits to come up with max tick

--HG--
extra : convert_revision : 08e9f7898b29fb9d063136529afb9b6abceab60c
2007-01-27 15:38:04 -05:00
Ali Saidi
63fdabf191 make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
    Add code to detect compiler and choose cflags based on detected compiler
    Fix zlib check to work with suncc
src/SConscript:
    split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
    use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
    add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
    use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
    include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
    remove dangling comma
src/arch/sparc/system.cc:
    dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
    use std namespace for string ops
src/arch/sparc/utility.hh:
    no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
    dummy returns to for suncc front end
src/base/cprintf.hh:
    use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
    don't need to define hash for suncc
src/base/hostinfo.cc:
    need stdio.h for sprintf
src/base/loader/object_file.cc:
    munmap is in std namespace not null
src/base/misc.hh:
    use M5 generic noreturn macros
    use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
    we need file.h for file flags
src/base/random.cc:
    mess with include files to make suncc happy
src/base/remote_gdb.cc:
    malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
    use std namespace for floor
src/base/stats/text.cc:
    include math.h for rint (cmath won't work)
src/base/time.cc:
    use suncc version of ctime_r
src/base/time.hh:
    change macro to work with both gcc and suncc
src/base/timebuf.hh:
    include cstring from memset and use std::
src/base/trace.hh:
    change variadic macros to be normal format
src/cpu/SConscript:
    add dummy returns where appropriate
src/cpu/activity.cc:
    include cstring for memset
src/cpu/exetrace.hh:
    include cstring fro memcpy
src/cpu/simple/base.hh:
    add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
    add dummy return where appropriate
src/dev/ide_atareg.h:
    make define work for both gnuc and suncc
src/dev/io_device.hh:
    add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
    include cstring for string ops
src/dev/sparc/mm_disk.cc:
    add dummy return where appropriate
    include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
    Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
    cast hastSets to double for log() call
src/mem/physical.cc:
    cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
    make define work for suncc and gnuc

--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-26 18:48:51 -05:00
Ali Saidi
b48a8fb347 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27 14:38:22 -05:00
Ali Saidi
b6dc902f6a Change MemoryAccess dprintfs to print the data as well
--HG--
extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
2006-12-27 14:32:26 -05:00
Steve Reinhardt
9d7db8bb2b Streamline Cache/Tags interface: get rid of redundant functions,
don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.

--HG--
extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
2006-12-18 23:07:52 -08:00
Steve Reinhardt
f655932700 No need to template prefetcher on cache TagStore type.
--HG--
rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc
extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
2006-12-18 21:53:06 -08:00
Steve Reinhardt
1428b0de7d Get rid of generic CacheTags object (fold back into Cache).
--HG--
extra : convert_revision : 8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
2006-12-18 20:47:12 -08:00
Lisa Hsu
4da37bcd1b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
2006-12-15 18:07:39 -05:00
Lisa Hsu
b93b32ec33 Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
2006-12-15 13:06:37 -05:00
Ali Saidi
4943d58272 Use my range_map to speed up findPort() in the bus. The snoop code could still use some work.
--HG--
extra : convert_revision : ba0a68bd378d68e4ebd80a101b965d36c8be1db9
2006-12-15 01:49:41 -05:00
Steve Reinhardt
d172e1576a Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).

--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-12-13 22:04:36 -08:00
Ali Saidi
ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-06 14:29:10 -05:00
Steve Reinhardt
1c28682cea Don't compress data on writebacks unless it's actually necessary.
--HG--
extra : convert_revision : 7a068e28f9ea2f6aab57be7133b47bda72d10302
2006-12-05 07:16:36 -08:00
Steve Reinhardt
5fbf3aa471 Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.

--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
2006-12-04 09:10:53 -08:00
Steve Reinhardt
6f94c3c8d7 Make cache compression policy a runtime virtual thing
instead of a template policy.

--HG--
extra : convert_revision : 6a4ac7a189a950390a973fdfce94f56190de92db
2006-12-02 22:22:58 -08:00
Gabe Black
5bdf4400b2 Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
    hand merge

--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
2006-11-29 17:34:20 -05:00
Ali Saidi
544f4b4d81 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3
2006-11-29 17:11:20 -05:00
Ali Saidi
b2eecd643c Add support for mmapped iprs to atomic cpu
src/arch/SConscript:
    add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
    make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
    miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
    add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
    allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits

--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
2006-11-29 17:11:10 -05:00
Kevin Lim
2b5fdf6033 Remove assertion. It's not needed and messes up writebacks when a 2 level cache is used in a uniprocessor setting.
--HG--
extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827
2006-11-28 11:41:08 -05:00
Gabe Black
d0f4a4c441 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
2006-11-24 14:08:43 -05:00
Ali Saidi
6e9cf9411f Merge zizzer:/bk/sparcfs
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : f540987901994fe9dc023587fd555efb2dbf24bf
2006-11-23 01:44:49 -05:00
Ali Saidi
271b9a5435 first cut at a sparc tlb
src/arch/sparc/SConscript:
    Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    update asi names for how they're listed in the supplement
    add asis
    add more asi functions
src/arch/sparc/isa_traits.hh:
    move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add mmu registers to tlb
    get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
    make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    first cut at sparc tlb
src/arch/sparc/vtophys.hh:
    pagatable nedes to be included here
src/mem/request.hh:
    add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
    fix incorrect definition of LL

--HG--
extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
2006-11-23 01:42:57 -05:00
Gabe Black
f85082e0a0 Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it.
--HG--
extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
2006-11-22 23:09:27 -05:00
Ron Dreslinski
28fd4ab39f Do a functional access to levels above on a read as a temporary solution for L2's in FS
Fix a small writeback bug when missing in the L2 in atomic mode

src/mem/bus.cc:
    Fix a comment to make sense
src/mem/cache/cache_impl.hh:
    Do a functional access to levels above on a read as a temporary solution for L2's in FS
    Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
    Update ref's for writeback changes

--HG--
extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
2006-11-22 20:20:38 -05:00
Gabe Black
04e6a3a07b Fix an assert to correctly make sure a request falls entirely inside a memory.
--HG--
extra : convert_revision : 71cf02edffbc7029666c0d9c97b67e1d32332758
2006-11-20 18:11:19 -05:00
Ron Dreslinski
c32f3056f9 Fix bugs around uni-coherence invalidates being propogated properly.
src/mem/bus.cc:
    Make it so that invalidates being sent from the responder up don't call the responder
    but they should also not Panic.
src/mem/packet.hh:
    If we don't have data in the packet, don't call deleteData:
    Example: InvalidateRequests never have data.

--HG--
extra : convert_revision : 18766bc9f3bb4d852ac651d094254d347abd1634
2006-11-14 17:15:05 -05:00
Ron Dreslinski
8155e61a60 Update atomic and functional paths for snoops as well
--HG--
extra : convert_revision : 566d73438efb87ca683e4dee23454d880db3dfc7
2006-11-14 01:38:42 -05:00
Ron Dreslinski
4135dd48ed Update bus bridges now that snoop ranges are passed properly
src/mem/bridge.cc:
    Update brdiges, now that snoop addresses are properly forwarded.
    Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT)
src/mem/bus.cc:
src/mem/bus.hh:
    Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once

--HG--
extra : convert_revision : 26cc9ee4429be45d4476fa435e0e9a54843c2509
2006-11-14 01:12:52 -05:00
Ron Dreslinski
903a618714 Fix a bug to handle the fact that a CPU can send Functional accesses while a sendTiming has not returned in the call stack.
src/mem/cache/base_cache.cc:
    Sometimes a functional access comes while waiting on a outstanding packet being sent.
    This could be because Timing CPU does some post processing on the recvTiming which send functional access.
    Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem
    system should remove them from outstanding lists and reinsert them if they fail in the sendTiming.

    I did the later, eventually we should consider doing the former if that is the correct behavior.

--HG--
extra : convert_revision : be41e0d2632369dca9d7c15e96e5576d7583fe6a
2006-11-13 22:37:22 -05:00
Ron Dreslinski
69e183941f If we didn't satisfy all targets, reset the packet we are requesting with.
--HG--
extra : convert_revision : 736372131b046eccf3520292fb3c086dc568d918
2006-11-13 21:34:25 -05:00
Ron Dreslinski
9b6fd56dd5 Fix some errors related to snooping and functional access in the bus
src/mem/bus.cc:
    Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
    Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.

--HG--
extra : convert_revision : 7276059c798a85cb9d138ccc5531298ecd055c13
2006-11-13 21:33:01 -05:00
Ron Dreslinski
6c5c51338d Fix problems with snoop ranges not working properly on functional accesses
src/mem/bus.cc:
    Actually return the snoop list when asked for it.
    Don't get stuck in infinite functional loops

--HG--
extra : convert_revision : 8e6dafbd10b30d48d28b6b5d4b464e8e8f6a3ddc
2006-11-13 19:56:34 -05:00
Ron Dreslinski
356a4f9f59 Since cpus now send out snoop ranges, remove it from the cache.
--HG--
extra : convert_revision : 82882eb131aa66eba9f281b64db21d5cbfefb1b9
2006-11-13 19:00:50 -05:00
Kevin Lim
3052632b68 Merge ktlim@zamp:./local/clean/tmp/test-regress
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
2006-11-12 21:57:58 -05:00
Ron Dreslinski
5edfaefc78 Physical memory overrides the tport version of recvFunctional, need to do the
check here for responses that match as well

--HG--
extra : convert_revision : 69c3628a381a9da885fab0272abf40c3411a5f0f
2006-11-12 09:30:12 -05:00
Ron Dreslinski
a200bccc20 Handle packets being deleted by lower level properly.
Fixes for Mem Leak associated with Writebacks.

src/mem/cache/miss/mshr_queue.cc:
    Fixes for Mem Leak associated with Writebacks. (Double Delete removed)

--HG--
extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
2006-11-12 09:06:15 -05:00
Ron Dreslinski
29cefcbf13 Don't insert reponses into the list more than once
If you get inserted in the front, reschedule the event

--HG--
extra : convert_revision : eccbacf5ec85600e5b68eb554fee2c0e2b65e965
2006-11-12 07:16:34 -05:00
Ron Dreslinski
11accacf7c Move code before a early return to make sure it is executed on all paths
--HG--
extra : convert_revision : cfdd5b6911422fbb733677c43d027aa4407fbc85
2006-11-12 06:44:05 -05:00
Ron Dreslinski
b22d390721 Yet another small bug in mem system related to flow control
src/mem/cache/cache_impl.hh:
    When upgrades change to readEx make sure to allocate the block
    Fix dprintf

--HG--
extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
2006-11-12 06:36:33 -05:00
Ron Dreslinski
c577665040 Fix functional access errors related to delayed respnoses in cachePort
src/mem/cache/base_cache.cc:
    On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
    Create a wrapper to toggle the hasData flag on delayed responses

--HG--
extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
2006-11-12 06:35:39 -05:00
Ron Dreslinski
f876bc2bf0 More fixes for functional accesses. It now makes the writeback memory leak to crash all configs.
Working on that now.

src/mem/cache/base_cache.cc:
    Keep a list of the responders so we can search them on functional accesses.
src/mem/cache/base_cache.hh:
    Properly put things on a list for responses so we can search the list.
    Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there)
src/mem/cache/cache_impl.hh:
    Properly return when the first read hit on a functional access.
    Make sure to call to check the other ports list of packets before forwarding it out.

--HG--
extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
2006-11-10 22:45:50 -05:00
Ron Dreslinski
9a6e896d3b Big fix for functional access, where we forgot to copy the last byte on write intersections.
src/mem/packet.cc:
    Make sure to copy the whole data (we were one byte short)
src/mem/tport.cc:
    Fix for the proper semantics of fixPacket

--HG--
extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8
2006-11-10 22:41:21 -05:00
Kevin Lim
73581bf801 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : 56cb7fe3be5b63bd89b48ac6cb88b47d13b4c137
2006-11-10 12:14:38 -05:00
Ali Saidi
cb172d0332 Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
    Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
    add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
    add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add option to try raw when nothing works
src/cpu/exetrace.cc:
    cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
    change the instruction to be 32 bits because it is
src/mem/physical.cc:
    fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
    Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
    Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
    add the ability to add Addr() together

--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-09 18:22:46 -05:00