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No need to template prefetcher on cache TagStore type.

Browse source 
--HG--
rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc
extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
This commit is contained in:
Steve Reinhardt 2006-12-18 21:53:06 -08:00
parent 1428b0de7d
commit f655932700
13 changed files with 192 additions and 208 deletions
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1
src/SConscript
View file

@ -114,7 +114,6 @@ base_sources = Split('''
mem/cache/miss/mshr_queue.cc
mem/cache/prefetch/base_prefetcher.cc
mem/cache/prefetch/ghb_prefetcher.cc
mem/cache/prefetch/prefetcher.cc
mem/cache/prefetch/stride_prefetcher.cc
mem/cache/prefetch/tagged_prefetcher.cc
mem/cache/tags/base_tags.cc

4
src/mem/cache/base_cache.hh vendored
View file

@ -692,6 +692,10 @@ class BaseCache : public MemObject
}
return true;
}
virtual bool inCache(Addr addr) = 0;
virtual bool inMissQueue(Addr addr) = 0;
};
#endif //__BASE_CACHE_HH__

17
src/mem/cache/cache.hh vendored
View file

@ -45,11 +45,10 @@
#include "mem/cache/base_cache.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/cache/miss/miss_buffer.hh"
#include "mem/cache/prefetch/prefetcher.hh"
//Forward decleration
class MSHR;
class BasePrefetcher;
/**
* A template-policy based cache. The behavior of the cache can be altered by
@ -119,7 +118,7 @@ class Cache : public BaseCache
Coherence *coherence;
/** Prefetcher */
Prefetcher<TagStore> *prefetcher;
BasePrefetcher *prefetcher;
/**
* The clock ratio of the outgoing bus.
@ -304,7 +303,7 @@ class Cache : public BaseCache
MissBuffer *missQueue;
Coherence *coherence;
BaseCache::Params baseParams;
Prefetcher<TagStore> *prefetcher;
BasePrefetcher*prefetcher;
bool prefetchAccess;
int hitLatency;
CompressionAlgorithm *compressionAlg;
@ -319,7 +318,7 @@ class Cache : public BaseCache
Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
BaseCache::Params params,
Prefetcher<TagStore> *_prefetcher,
BasePrefetcher *_prefetcher,
bool prefetch_access, int hit_latency,
bool do_fast_writes,
bool store_compressed, bool adaptive_compression,
@ -450,6 +449,14 @@ class Cache : public BaseCache
* @return The estimated completion time.
*/
Tick snoopProbe(PacketPtr &pkt);
bool inCache(Addr addr) {
return (tags->findBlock(addr) != 0);
}
bool inMissQueue(Addr addr) {
return (missQueue->findMSHR(addr) != 0);
}
};
#endif // __CACHE_HH__

70
src/mem/cache/cache_builder.cc vendored
View file

@ -197,7 +197,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
#define BUILD_CACHE(TAGS, tags, c) \
do { \
Prefetcher<TAGS> *pf; \
BasePrefetcher *pf; \
if (pf_policy == "tagged") { \
BUILD_TAGGED_PREFETCHER(TAGS); \
} \
@ -314,55 +314,55 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
} while (0)
#if defined(USE_TAGGED)
#define BUILD_TAGGED_PREFETCHER(t) pf = new \
TaggedPrefetcher<t >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree)
#define BUILD_TAGGED_PREFETCHER(t) \
pf = new TaggedPrefetcher(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree)
#else
#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
#endif
#if defined(USE_STRIDED)
#define BUILD_STRIDED_PREFETCHER(t) pf = new \
StridePrefetcher<t >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree, \
prefetch_use_cpu_id)
#define BUILD_STRIDED_PREFETCHER(t) \
pf = new StridePrefetcher(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree, \
prefetch_use_cpu_id)
#else
#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
#endif
#if defined(USE_GHB)
#define BUILD_GHB_PREFETCHER(t) pf = new \
GHBPrefetcher<t >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree, \
prefetch_use_cpu_id)
#define BUILD_GHB_PREFETCHER(t) \
pf = new GHBPrefetcher(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree, \
prefetch_use_cpu_id)
#else
#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
#endif
#if defined(USE_TAGGED)
#define BUILD_NULL_PREFETCHER(t) pf = new \
TaggedPrefetcher<t >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree)
#define BUILD_NULL_PREFETCHER(t) \
pf = new TaggedPrefetcher(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
prefetch_data_accesses_only, \
prefetch_latency, \
prefetch_degree)
#else
#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
#endif

4
src/mem/cache/cache_impl.hh vendored
View file

@ -49,7 +49,7 @@
#include "mem/cache/cache.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/prefetch/prefetcher.hh"
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "sim/sim_exit.hh" // for SimExitEvent
@ -88,8 +88,6 @@ Cache(const std::string &_name,
missQueue->setPrefetcher(prefetcher);
coherence->setCache(this);
prefetcher->setCache(this);
prefetcher->setTags(tags);
prefetcher->setBuffer(missQueue);
invalidateReq = new Request((Addr) NULL, blkSize, 0);
invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
}

26
src/mem/cache/prefetch/base_prefetcher.cc vendored
View file

@ -102,6 +102,26 @@ BasePrefetcher::regStats(const std::string &name)
;
}
inline bool
BasePrefetcher::inCache(Addr addr)
{
if (cache->inCache(addr)) {
pfCacheHit++;
return true;
}
return false;
}
inline bool
BasePrefetcher::inMissQueue(Addr addr)
{
if (cache->inMissQueue(addr)) {
pfMSHRHit++;
return true;
}
return false;
}
PacketPtr
BasePrefetcher::getPacket()
{
@ -118,7 +138,7 @@ BasePrefetcher::getPacket()
pkt = *pf.begin();
pf.pop_front();
if (!cacheCheckPush) {
keepTrying = inCache(pkt);
keepTrying = cache->inCache(pkt->getAddr());
}
if (pf.empty()) {
cache->clearMasterRequest(Request_PF);
@ -190,7 +210,7 @@ BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time)
//Check if it is already in the cache
if (cacheCheckPush) {
if (inCache(prefetch)) {
if (cache->inCache(prefetch->getAddr())) {
addr++;
delay++;
continue;
@ -198,7 +218,7 @@ BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time)
}
//Check if it is already in the miss_queue
if (inMissQueue(prefetch->getAddr())) {
if (cache->inMissQueue(prefetch->getAddr())) {
addr++;
delay++;
continue;

13
src/mem/cache/prefetch/base_prefetcher.hh vendored
View file

@ -36,10 +36,13 @@
#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
#include "mem/packet.hh"
#include <list>
#include "base/statistics.hh"
#include "mem/packet.hh"
class BaseCache;
class BasePrefetcher
{
protected:
@ -95,6 +98,10 @@ class BasePrefetcher
void handleMiss(PacketPtr &pkt, Tick time);
bool inCache(Addr addr);
bool inMissQueue(Addr addr);
PacketPtr getPacket();
bool havePending()
@ -106,10 +113,6 @@ class BasePrefetcher
std::list<Addr> &addresses,
std::list<Tick> &delays) = 0;
virtual bool inCache(PacketPtr &pkt) = 0;
virtual bool inMissQueue(Addr address) = 0;
std::list<PacketPtr>::iterator inPrefetch(Addr address);
};

42
src/mem/cache/prefetch/ghb_prefetcher.cc vendored
View file

@ -31,16 +31,44 @@
/**
* @file
* GHB Prefetcher template instantiations.
* GHB Prefetcher implementation.
*/
#include "mem/cache/tags/lru.hh"
#include "mem/cache/prefetch/ghb_prefetcher.hh"
#include "arch/isa_traits.hh"
// Template Instantiations
#ifndef DOXYGEN_SHOULD_SKIP_THIS
void
GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
int cpuID = pkt->req->getCpuNum();
if (!useCPUId) cpuID = 0;
template class GHBPrefetcher<LRU >;
#endif //DOXYGEN_SHOULD_SKIP_THIS
int new_stride = blkAddr - last_miss_addr[cpuID];
int old_stride = last_miss_addr[cpuID] -
second_last_miss_addr[cpuID];
second_last_miss_addr[cpuID] = last_miss_addr[cpuID];
last_miss_addr[cpuID] = blkAddr;
if (new_stride == old_stride) {
for (int d=1; d <= degree; d++) {
Addr newAddr = blkAddr + d * new_stride;
if (this->pageStop &&
(blkAddr & ~(TheISA::VMPageSize - 1)) !=
(newAddr & ~(TheISA::VMPageSize - 1)))
{
//Spanned the page, so now stop
this->pfSpanPage += degree - d + 1;
return;
}
else
{
addresses.push_back(newAddr);
delays.push_back(latency);
}
}
}
}

59
src/mem/cache/prefetch/ghb_prefetcher.hh vendored
View file

@ -30,31 +30,18 @@
/**
* @file
* Describes a ghb prefetcher based on template policies.
* Describes a ghb prefetcher.
*/
#ifndef __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
#define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
#include "base/misc.hh" // fatal, panic, and warn
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "mem/cache/prefetch/prefetcher.hh"
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
* storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
template <class TagStore>
class GHBPrefetcher : public Prefetcher<TagStore>
class GHBPrefetcher : public BasePrefetcher
{
protected:
MissBuffer* mq;
TagStore* tags;
Addr second_last_miss_addr[64/*MAX_CPUS*/];
Addr last_miss_addr[64/*MAX_CPUS*/];
@ -67,48 +54,16 @@ class GHBPrefetcher : public Prefetcher<TagStore>
GHBPrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree, bool useCPUId)
:Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
: BasePrefetcher(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
{
}
~GHBPrefetcher() {}
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
int cpuID = pkt->req->getCpuNum();
if (!useCPUId) cpuID = 0;
int new_stride = blkAddr - last_miss_addr[cpuID];
int old_stride = last_miss_addr[cpuID] -
second_last_miss_addr[cpuID];
second_last_miss_addr[cpuID] = last_miss_addr[cpuID];
last_miss_addr[cpuID] = blkAddr;
if (new_stride == old_stride) {
for (int d=1; d <= degree; d++) {
Addr newAddr = blkAddr + d * new_stride;
if (this->pageStop &&
(blkAddr & ~(TheISA::VMPageSize - 1)) !=
(newAddr & ~(TheISA::VMPageSize - 1)))
{
//Spanned the page, so now stop
this->pfSpanPage += degree - d + 1;
return;
}
else
{
addresses.push_back(newAddr);
delays.push_back(latency);
}
}
}
}
std::list<Tick> &delays);
};
#endif // __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__

58
src/mem/cache/prefetch/stride_prefetcher.cc vendored
View file

@ -34,13 +34,59 @@
* Stride Prefetcher template instantiations.
*/
#include "mem/cache/tags/lru.hh"
#include "mem/cache/prefetch/stride_prefetcher.hh"
// Template Instantiations
#ifndef DOXYGEN_SHOULD_SKIP_THIS
void
StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
int cpuID = pkt->req->getCpuNum();
if (!useCPUId) cpuID = 0;
template class StridePrefetcher<LRU >;
/* Scan Table for IAddr Match */
/* std::list<strideEntry*>::iterator iter;
for (iter=table[cpuID].begin();
iter !=table[cpuID].end();
iter++) {
if ((*iter)->IAddr == pkt->pc) break;
}
#endif //DOXYGEN_SHOULD_SKIP_THIS
if (iter != table[cpuID].end()) {
//Hit in table
int newStride = blkAddr - (*iter)->MAddr;
if (newStride == (*iter)->stride) {
(*iter)->confidence++;
}
else {
(*iter)->stride = newStride;
(*iter)->confidence--;
}
(*iter)->MAddr = blkAddr;
for (int d=1; d <= degree; d++) {
Addr newAddr = blkAddr + d * newStride;
if (this->pageStop &&
(blkAddr & ~(TheISA::VMPageSize - 1)) !=
(newAddr & ~(TheISA::VMPageSize - 1)))
{
//Spanned the page, so now stop
this->pfSpanPage += degree - d + 1;
return;
}
else
{
addresses.push_back(newAddr);
delays.push_back(latency);
}
}
}
else {
//Miss in table
//Find lowest confidence and replace
}
*/
}

77
src/mem/cache/prefetch/stride_prefetcher.hh vendored
View file

@ -30,31 +30,18 @@
/**
* @file
* Describes a strided prefetcher based on template policies.
* Describes a strided prefetcher.
*/
#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
#include "base/misc.hh" // fatal, panic, and warn
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "mem/cache/prefetch/prefetcher.hh"
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
* storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
template <class TagStore>
class StridePrefetcher : public Prefetcher<TagStore>
class StridePrefetcher : public BasePrefetcher
{
protected:
MissBuffer* mq;
TagStore* tags;
class strideEntry
{
public:
@ -84,66 +71,16 @@ class StridePrefetcher : public Prefetcher<TagStore>
StridePrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree, bool useCPUId)
:Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
: BasePrefetcher(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
{
}
~StridePrefetcher() {}
void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
int cpuID = pkt->req->getCpuNum();
if (!useCPUId) cpuID = 0;
/* Scan Table for IAddr Match */
/* std::list<strideEntry*>::iterator iter;
for (iter=table[cpuID].begin();
iter !=table[cpuID].end();
iter++) {
if ((*iter)->IAddr == pkt->pc) break;
}
if (iter != table[cpuID].end()) {
//Hit in table
int newStride = blkAddr - (*iter)->MAddr;
if (newStride == (*iter)->stride) {
(*iter)->confidence++;
}
else {
(*iter)->stride = newStride;
(*iter)->confidence--;
}
(*iter)->MAddr = blkAddr;
for (int d=1; d <= degree; d++) {
Addr newAddr = blkAddr + d * newStride;
if (this->pageStop &&
(blkAddr & ~(TheISA::VMPageSize - 1)) !=
(newAddr & ~(TheISA::VMPageSize - 1)))
{
//Spanned the page, so now stop
this->pfSpanPage += degree - d + 1;
return;
}
else
{
addresses.push_back(newAddr);
delays.push_back(latency);
}
}
}
else {
//Miss in table
//Find lowest confidence and replace
}
*/ }
std::list<Tick> &delays);
};
#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__

12
src/mem/cache/prefetch/tagged_prefetcher_impl.hh → src/mem/cache/prefetch/tagged_prefetcher.cc vendored
View file

@ -36,20 +36,18 @@
#include "arch/isa_traits.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
template <class TagStore>
TaggedPrefetcher<TagStore>::
TaggedPrefetcher::
TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree)
:Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree)
: BasePrefetcher(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree)
{
}
template <class TagStore>
void
TaggedPrefetcher<TagStore>::
TaggedPrefetcher::
calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{

17
src/mem/cache/prefetch/tagged_prefetcher.hh vendored
View file

@ -30,29 +30,18 @@
/**
* @file
* Describes a tagged prefetcher based on template policies.
* Describes a tagged prefetcher.
*/
#ifndef __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
#define __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
#include "mem/cache/prefetch/prefetcher.hh"
#include "mem/cache/prefetch/base_prefetcher.hh"
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
* storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
template <class TagStore>
class TaggedPrefetcher : public Prefetcher<TagStore>
class TaggedPrefetcher : public BasePrefetcher
{
protected:
MissBuffer* mq;
TagStore* tags;
Tick latency;
int degree;