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Author SHA1 Message Date
Gabe Black
f33bab2386 Cleaned up the decoder slightly. 
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
 2006-10-26 22:47:17 -04:00
Gabe Black
f88b90dd56 Added a few functions to stuff values into bitfields in an instruction. 
--HG--
extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
 2006-10-26 20:25:22 -04:00
Gabe Black
d1b30102fd Changed the number of register windows to be more realistic. 
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
 2006-10-26 20:24:01 -04:00
Gabe Black
5024b20278 Got rid of some debug output 
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
 2006-10-26 20:23:00 -04:00
Gabe Black
e441be1b82 Change the default function from setMiscRegWithEffect to setMiscReg 
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
 2006-10-26 20:22:23 -04:00
Gabe Black
93b3176d4e Fixed the priv instruction format. 
src/arch/sparc/isa/formats/priv.isa:
    Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
    Added an Hpstate operand, and adjusted the numbering.

--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
 2006-10-25 17:58:44 -04:00
Gabe Black
99d9d40e6c Implemented the saved and restored instructions, fixed up register window instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction. 
--HG--
extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
 2006-10-25 17:54:14 -04:00
Gabe Black
047455625e Fixed the bitfield FCN to include the right bits. 
--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
 2006-10-25 17:50:39 -04:00
Gabe Black
e2eef8859b Implemented the SPARC fill and spill handlers. 
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
    Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.

--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
 2006-10-25 17:49:41 -04:00
Gabe Black
1b1495930c Replace the Alpha No op with a SPARC one. 
--HG--
extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
 2006-10-24 15:50:41 -04:00
Gabe Black
ef8b7713ca Minor compile fix. Not sure why this is broken. 
--HG--
extra : convert_revision : 6f181b15f37114ca0a3965cabcb2036bd2f97916
 2006-10-23 11:17:59 -04:00
Gabe Black
18b2d94b8c Move around more SPARC memory code, and make block memory operations work with the timing cpu 
--HG--
extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
 2006-10-23 11:17:15 -04:00
Gabe Black
466c387318 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
 2006-10-23 09:44:58 -04:00
Gabe Black
274d2670a1 Add reference outputs for SPARC on the atomic timing cpu model 
--HG--
extra : convert_revision : b64ff7c05504da6112631baaae8f0d927469e16f
 2006-10-23 07:57:16 -04:00
Gabe Black
20208d00e6 Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 
--HG--
rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa
rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa
extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
 2006-10-23 07:55:52 -04:00
Gabe Black
e9908e3c85 Don't let interupts interupt microcode at undesired points. 
--HG--
extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
 2006-10-23 02:39:02 -04:00
Gabe Black
a8973c6054 Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <inttypes.hh> 
--HG--
extra : convert_revision : c1e46c012a26cdb0603416f8e8a99e0ecb1c09bc
 2006-10-23 02:37:54 -04:00
Gabe Black
f31d73a433 Start making memory ops work with InitiateAcc and CompleteAcc, and some minor cleanups 
--HG--
extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
 2006-10-23 02:36:46 -04:00
Gabe Black
3d6ff82552 Change the default constructors to take ExtMachInsts rather than regular MachInsts 
--HG--
extra : convert_revision : 8fa34f82e0cbf5ce81775d572b182826c578581f
 2006-10-23 02:32:58 -04:00
Steve Reinhardt
d2856c2fde Add mutex test to Benchmarks.py. 
--HG--
extra : convert_revision : 9b4f1ce9a181ac5a01e5b6a68067079969dfe9ce
 2006-10-22 12:52:58 -04:00
Steve Reinhardt
968311d096 Another missing case in a switch (like Nate's earlier fix). 
--HG--
extra : convert_revision : b2f195c29861a09e9dd99aefcf4a173be2f8c97c
 2006-10-22 12:51:49 -04:00
Steve Reinhardt
810dee6e98 Have tracediff print warning if no traceflags are set. 
Elaborate on description a bit.

--HG--
extra : convert_revision : 2649961b53d6fb2774ddfb60219415ae4251db2d
 2006-10-22 12:51:00 -04:00
Steve Reinhardt
5e2263fc52 Small bug fixes for timing LL/SC. Better now but 
not necessarily 100% there yet.

src/mem/cache/cache_impl.hh:
    Generate response packet on failed store conditional.
src/mem/packet.hh:
    Clear packet flags when reinitializing.
    (SATISFIED in particular is one we don't want to leave set.)

--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
 2006-10-21 23:35:00 -07:00
Steve Reinhardt
0159529343 Add Quiesce trace flag to track CPU quiesce/wakeup events. 
--HG--
extra : convert_revision : 23be99d0fe6e2184523efe5d9e0a1ac7bf19d087
 2006-10-21 23:32:14 -07:00
Steve Reinhardt
883ed108e4 Just give up if a store conditional misses completely 
in the cache (don't treat as normal write miss).

--HG--
extra : convert_revision : c030eb6ba25318cae422e4da31e3b802049c8c74
 2006-10-21 17:19:33 -07:00
Steve Reinhardt
82e90bf5e0 Fix formatting that got screwed up when tabs were removed. 
--HG--
extra : convert_revision : 98596542a5774fe010e25632836ce92b66779f53
 2006-10-21 13:54:48 -07:00
Steve Reinhardt
1e6aa0d0d0 Refactor coherence state table initialization. 
--HG--
extra : convert_revision : eb36dd2cc1463e5076f4758a59cf68cc6b2bafc5
 2006-10-21 13:43:14 -07:00
Steve Reinhardt
fdad936f79 Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-llsc

--HG--
extra : convert_revision : 157d07cc56e8ea68741d1b8536a9856488cb4a69
 2006-10-21 11:41:53 -07:00
Steve Reinhardt
e70f5507e2 Get rid of unused handleTargets() function. 
--HG--
extra : convert_revision : 90032c3831d10e98c6453cd6144f9c00b9f97219
 2006-10-21 11:38:23 -07:00
Steve Reinhardt
3ac1ca8ff6 Tweak a few things for better page fault debugging. 
src/sim/faults.cc:
    Fix fault message.
src/kern/tru64/tru64.hh:
    Add DPRINTF to see where new thread stacks are allocated.
src/arch/alpha/faults.cc:
    Add print statement so we know what the faulting address is in SE mode.

--HG--
extra : convert_revision : 6eb2b513c339496a0d013b7e914953a0a066c12d
 2006-10-21 05:28:05 -04:00
Steve Reinhardt
0e121bc14f Updated to work with new command line argument ordering. 
Note that command line syntax has totally changed as a result.
See comments for more details.

--HG--
extra : convert_revision : bdb6e27abd2da83c7468dfe2a95e8bf54757ac6c
 2006-10-21 02:24:27 -07:00
Nathan Binkert
5e34c3fe13 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  iceaxe.:/Volumes/work/research/m5/incoming

--HG--
extra : convert_revision : c9153e5dca1d1f46a34770c645761d7b0419e8ce
 2006-10-21 00:32:09 -07:00
Nathan Binkert
dff1a022b8 Missing case 
--HG--
extra : convert_revision : 128896dd1a654fe9a02e2c07ef6ce6799b62f21f
 2006-10-21 00:31:46 -07:00
Ron Dreslinski
30cd2298df Add some default options, point it to the /dist version of the splash benchmarks 
--HG--
extra : convert_revision : cd3b4f395b360d646b8b60464768eaad0fd110a4
 2006-10-20 21:13:10 -04:00
Ron Dreslinski
e855a7e6f2 Merge zizzer:/bk/newmem 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 4678ce5fb0dc29a28d9cd21e687f9cee967d21fa
 2006-10-20 20:04:45 -04:00
Ron Dreslinski
e198e58e1e Clean up splash2 so it works in v2.0 
configs/splash2/run.py:
    Update the splash2 file

--HG--
extra : convert_revision : b57ef1ab4b8fd1eaf281358db623b7581b96546b
 2006-10-20 19:53:52 -04:00
Gabe Black
0b5cf4ba6e Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
 2006-10-20 16:39:47 -04:00
Nathan Binkert
6c6b78126a Construct a correct value of PYTHONHOME from the interpreter 
running SCons, make it into a sticky option that can be
overridden at build time, and set it up before the interpreter
is started.  Also, fix the code that turns sticky options into
config/*.hh so that it works with types other than bool.

--HG--
extra : convert_revision : 602398b35d4da4e813f78865678ed348fdea7270
 2006-10-20 11:37:59 -07:00
Ron Dreslinski
ad783962c5 Give physical memory some latency to stress the system 
--HG--
extra : convert_revision : 3ca32ff9140770d0774cac5e82807a0574db09dd
 2006-10-20 13:36:26 -04:00
Ron Dreslinski
316e0fa879 Add a config file in the example with the memtester and some parser options. 
--HG--
extra : convert_revision : e70ccc3de4f7a3ae20ff9ec672853ee1555ed41b
 2006-10-20 13:32:24 -04:00
Ron Dreslinski
ba24ce6bb6 Get rid of a variable put back by merge. 
--HG--
extra : convert_revision : 5ddb6ae5d5412f062c07c16a27b79483430b5f22
 2006-10-20 13:05:39 -04:00
Ron Dreslinski
54ed57cc4c Merge zizzer:/bk/newmem 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/tport.cc:
    Merge PacketPtr changes

--HG--
extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
 2006-10-20 13:04:59 -04:00
Ron Dreslinski
28e9641c2c Use fixPacket function everywhere. 
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
 2006-10-20 13:01:21 -04:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere 
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
 2006-10-20 00:10:12 -07:00
Nathan Binkert
7245d4530d refactor code for the packet, get rid of packet_impl.hh 
and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
 2006-10-19 23:38:45 -07:00
Nathan Binkert
5b246a0567 initialize end, clean up loop 
--HG--
extra : convert_revision : e1c107f0c0fd5d535acd2d6c43571a5df57c9ed3
 2006-10-19 23:35:59 -07:00
Nathan Binkert
b937d54510 Fix compile of m5.fast 
--HG--
extra : convert_revision : a8a37c318e55e48e697e4aaba339328f000b3f60
 2006-10-19 23:34:59 -07:00
Steve Reinhardt
0d2908a584 Delete unused file src/mem/cache.hh 
--HG--
extra : convert_revision : 11bd043bb72eef0239fa60155e1f5a5e02de7cbc
 2006-10-19 22:59:38 -07:00
Steve Reinhardt
3772e4fc97 m5term: assume localhost if host name not provided. 
util/term/term.c:
    Reindent.
util/term/term.c:
    Assume localhost if only port number is given on command line.

--HG--
extra : convert_revision : 768e61a56339a0795ca258cca788e9a2c20cbaae
 2006-10-19 21:42:30 -07:00
Ron Dreslinski
780aa0a0eb Fix corner case on assertion. 
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
 2006-10-19 21:26:46 -04:00