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Author SHA1 Message Date
Gabe Black f26051eb1a MIPS: Take advantage of new PCState syntax. 2010-12-08 10:45:14 -08:00
Gabe Black 7f3f90f71d POWER: Take advantage of new PCState syntax. 2010-12-08 10:33:03 -08:00
Gabe Black f01d2efe8a SPARC: Take advantage of new PCState syntax. 2010-12-08 00:27:43 -08:00
Gabe Black d3e021820e X86: Take advantage of new PCState syntax. 2010-12-08 00:27:23 -08:00
Gabe Black 4c9b023a7a ISA: Get the parser to support pc state components more elegantly. 2010-12-07 23:08:05 -08:00
Ali Saidi 42ba158479 O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg). 
The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.
 2010-12-07 16:19:57 -08:00
Ali Saidi e681c0f7b3 O3: Support squashing all state after special instruction 
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply
marking the instruction as Serializing isn't enough beacuse that only
stops rename. This provides a mechanism to squash all the instructions
and refetch them
 2010-12-07 16:19:57 -08:00
Giacomo Gabrielli 719f9a6d4f O3: Make all instructions that write a misc. register not perform the write until commit. 
ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.

Added aliases for ARM FP exceptions and saturation flags in FPSCR.  Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes.  Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
 2010-12-07 16:19:57 -08:00
Min Kyu Jeong 4bbdd6ceb2 O3: Support SWAP and predicated loads/store in ARM. 2010-12-07 16:19:57 -08:00
Ali Saidi 21bfbd422c ARM: Support switchover with hardware table walkers 2010-12-07 16:19:57 -08:00
Nilay Vaish 658849d101 ruby: Converted old ruby debug calls to M5 debug calls 
This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.
 2010-12-01 11:30:04 -08:00
Ali Saidi 0f039fe447 IGbE: return 0 on an invalid descriptor size instead of -1. 
Asserts where descSize() get called with assert if we end up returning
0.
 2010-11-26 20:47:23 -05:00
Gabe Black 7f6ca0981f Copyright: Add AMD copyright to the param changes I just made. 2010-11-23 17:08:41 -05:00
Gabe Black b3de4855c3 Params: Add parameter types for IP addresses in various forms. 
New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.
 2010-11-23 15:54:43 -05:00
Gabe Black 40d434d551 X86: Loosen an assert for x86 and connect the APIC ports when caches are used. 2010-11-23 06:11:50 -05:00
Gabe Black 3cd349f443 X86: Obey the PCD (cache disable) bit in the page tables. 2010-11-23 06:10:17 -05:00
Gabe Black c8c921b9db X86: Mark IO space accesses as uncachable. 2010-11-22 05:49:03 -05:00
Gabe Black 6a00519e73 IDE,X86: Fix IDE controller BAR configuration for x86. 2010-11-22 02:33:47 -05:00
Nathan Binkert 4d9ff1954b random: small comment about our random number generator and its origin 2010-11-20 12:12:27 -08:00
Ali Saidi 34a8e37c13 SE: Fix simulating more than 4GB of RAM in SE mode 
This change removes some dead code in PhysicalMemory, uses a 64 bit type
for the page pointer in System (instead of 32 bit) and cleans up some style.
 2010-11-19 18:01:01 -06:00
Ali Saidi e1b9a815dd SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
Gabe Black 92655b6399 O3: Fix fp destination register flattening, and index offset adjusting. 
This change makes O3 flatten floating point destination registers, and also
fixes misc register flattening so that it's correctly repositioned relative to
the resized regions for integer and floating point indices.

It also fixes some overly long lines.
 2010-11-18 13:11:36 -05:00
Gabe Black 8b9b85e92c O3: Make O3 support variably lengthed instructions. 2010-11-15 19:37:03 -08:00
Ali Saidi 776c075917 O3: reset architetural state by calling clear() 2010-11-15 14:04:05 -06:00
Ali Saidi 5f59e195d6 ARM: Add comment about the organization of the IT state register 2010-11-15 14:04:05 -06:00
Giacomo Gabrielli 0058927190 CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
Min Kyu Jeong 745df74fe0 O3: prevent a squash when completeAcc() modifies misc reg through TC. 
This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc() methods
 2010-11-15 14:04:04 -06:00
Ali Saidi 4a1814bd52 ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed. 
Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
 2010-11-15 14:04:04 -06:00
Ali Saidi d4767f440a SCons: Cleanup SCons output during compile 2010-11-15 14:04:04 -06:00
William Wang 6fbea15064 ARM: Add a Keyboard Mouse Interface controller 2010-11-15 14:04:03 -06:00
William Wang fc1eeafc94 ARM: Implement a CLCD Frame buffer 2010-11-15 14:04:03 -06:00
William Wang 80db6a5ecb ARM: Add support for GDB on ARM 
--HG--
rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc
 2010-11-15 14:04:03 -06:00
Ali Saidi 06864386a1 ARM: Make utility.hh meet style guidelines 2010-11-15 14:04:03 -06:00
Ali Saidi d7b8efa0df ARM: Add support for a dumb IDE controller 2010-11-15 14:04:03 -06:00
Ali Saidi 13931b9b82 ARM: Cache the misc regs at the TLB to limit readMiscReg() calls. 2010-11-15 14:04:03 -06:00
Ali Saidi 4c2e5c282b ARM: Add support for switching CPUs 2010-11-15 14:04:03 -06:00
Ali Saidi 08c5673d56 ARM: Use the correct delete operator for RFE 2010-11-15 14:04:03 -06:00
Ali Saidi 50431f4eab ARM: Fix SRS instruction to micro-code memory operation and register update. 
Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.
 2010-11-15 14:04:03 -06:00
Ali Saidi 16f210da37 CPU: Fix bug when a split transaction is issued to a faster cache 
In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
 2010-11-15 14:04:03 -06:00
Ali Saidi 265e145db2 ARM: Do something predictable for an UNPREDICTABLE branch. 2010-11-15 14:04:03 -06:00
Gabe Black 46472279c0 Params: Fix an off by one error and a misleading comment. 2010-11-11 11:58:09 -08:00
Gabe Black 3c237f44c9 SimObject: Add a comment near clear_child that it's unlikely to be called. 2010-11-11 11:41:13 -08:00
Gabe Black cdc585e0e8 SPARC: Clean up some historical style issues. 2010-11-11 02:03:58 -08:00
Gabe Black 2fd9dc19cd SimObject: Use "self" when calling the clear_child method. 2010-11-09 10:45:02 -08:00
Gabe Black 388124492e X86: Fix X86_FS compilation. 2010-11-08 12:43:38 -08:00
Ali Saidi 057b451773 ARM: Add some TLB statistics for ARM 2010-11-08 13:58:25 -06:00
Ali Saidi a1e8225975 ARM: Add checkpointing support 2010-11-08 13:58:25 -06:00
Ali Saidi 432fa0aad6 ARM: Add support for M5 ops in the ARM ISA 2010-11-08 13:58:24 -06:00
Ali Saidi 0f2bbe15dd ARM: Keep the warnings to a minimum. 
These warnings still need to be addresses, but pages of them is
counterproductive.
 2010-11-08 13:58:24 -06:00
Ali Saidi c779af4e12 Mem: Finish half-baked support for mmaping file in physmem. 
Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.
 2010-11-08 13:58:24 -06:00