Commit graph

4133 commits

Author SHA1 Message Date
Gabe Black
ecc1066f43 Added a missing include.
--HG--
extra : convert_revision : 15a1b49ff9e0a1a15bd2500bec9ec9bc95ee5898
2007-03-05 14:48:18 +00:00
Gabe Black
ec8b49cc5f Added a missing include.
--HG--
extra : convert_revision : 62583e5a5647913fb36e1aae265e8ac52a165829
2007-03-05 14:47:42 +00:00
Gabe Black
8a33c8dce4 Fix up the remote gdb include gaurds so it doesn't use the same symbol as Alpha does.
--HG--
extra : convert_revision : b75dbdd95ceb4ec71275588a5cf8e6b614cf4539
2007-03-05 14:46:49 +00:00
Gabe Black
30e700600c x86 register file includes.
--HG--
extra : convert_revision : c00a077dd7ae8f6b48c6939034be244bcf48d715
2007-03-05 12:23:14 +00:00
Gabe Black
b9b29525a6 Include the x86 specific traits file.
--HG--
extra : convert_revision : bcf448aedd832022527cc972f7a1f0433987c564
2007-03-05 12:21:20 +00:00
Gabe Black
9e93feea10 Stub x86 Fault class which just panics.
--HG--
extra : convert_revision : abfcf4005ec636b1e6c085515b63c1d8e69e3370
2007-03-05 12:20:34 +00:00
Gabe Black
385eb586ce A new file for x86 specific parameters. This could be implemented as a sim object?
--HG--
extra : convert_revision : 51757435bb0b20132f3ec5782db31382bb2cca18
2007-03-05 12:19:54 +00:00
Gabe Black
be29612fbe Add in a declaration of class Checkpoint rather than expecting it to come from some other include.
--HG--
extra : convert_revision : adbd4899508e3d30959a504a48402f01d1187099
2007-03-05 12:19:11 +00:00
Gabe Black
6a19b64de2 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : b585cea2221377eb2fceea8976c46a17c0034f51
2007-03-05 11:00:44 +00:00
Nathan Binkert
ba042842c6 Don't use the exact same name as a system header #define
--HG--
extra : convert_revision : 099e380395fc1fdaef993b019d3d4e596e8076c2
2007-03-04 19:26:49 -08:00
Ali Saidi
a81143f06a add a sparc fs regression
src/dev/sparc/iob.cc:
    don't warn on cpu restart/idle/halt stuff
tests/SConscript:
    add sparc target in test Sconscript
util/regress:
    Add SPARC_FS target in regress

--HG--
extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
2007-03-03 22:45:26 -05:00
Ali Saidi
82874eefca Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03 19:03:22 -05:00
Ali Saidi
1694c65ba1 Add Iob and remove the fake device
configs/common/FSConfig.py:
    add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy

--HG--
extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
2007-03-03 19:02:31 -05:00
Ali Saidi
36f43ff6a5 Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03 17:22:47 -05:00
Nathan Binkert
61178c8de2 include signal.h
--HG--
extra : convert_revision : 9b5ad2704dfd63a1aa8ad0e4275fd0e3a7d32d6d
2007-03-03 12:26:14 -05:00
Gabe Black
5498d52985 Filled in with basic x86 stuff. Some things are missing, wrong, or nonsensical for x86.
--HG--
extra : convert_revision : 2f7845db6d65b353985b474f7012cfbbaece6a39
2007-03-03 17:19:52 +00:00
Gabe Black
0150515ac3 Filled in with basic x86 information. Some things are missing, wrong, or non-sensical in x86.
--HG--
extra : convert_revision : bba78db3667e214c95bb127872d3fdf546619703
2007-03-03 17:18:29 +00:00
Gabe Black
10871b7342 Add build hooks for x86.
--HG--
extra : convert_revision : 438eb74f14e6ea60bab5012110f3946c9213786e
2007-03-03 16:01:48 +00:00
Nathan Binkert
e78bcd94a0 Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.int.chaotic.net:/Users/nate/work/m5/outgoing

--HG--
extra : convert_revision : b3d48721ead389fa807c0d5392039d4fc71a252e
2007-03-03 07:47:00 -08:00
Nathan Binkert
53f5fda5de Do the default argument stuff in python
--HG--
extra : convert_revision : 235f85e611a669401c6ddfbdf14244e80eb55888
2007-03-03 07:45:55 -08:00
Gabe Black
68ad153309 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32

--HG--
extra : convert_revision : bbd0def502e423e64e2c4f6415a4b043b60c7f90
2007-03-03 06:24:01 +00:00
Nathan Binkert
ffe6bebb05 Factor code out of main.cc and main.i into a bunch of files
so things are organized in a more sensible manner.  Take apart
finalInit and expose the individual functions which are now
called from python.  Make checkpointing a bit easier to use.

--HG--
extra : convert_revision : f470ddabbb47103e7b4734ef753c40089f2dcd9d
2007-03-02 22:24:00 -08:00
Gabe Black
23dc5099a4 Implement the _llseek syscall. It's Linux only, so we'll actually use the lseek syscall.
--HG--
extra : convert_revision : cccfd5efddbba527c6fb4e07ad2ab235a2670918
2007-03-03 03:34:55 +00:00
Gabe Black
477afcaf5b Fix some issues with 32 bit processes.
--HG--
extra : convert_revision : b01b38bbf185f2279134db4976a9bdb3e381a670
2007-03-03 03:34:54 +00:00
Gabe Black
4b4b46ea90 Keep around which input set was used for a benchmark, and make vortex work with SPARC.
--HG--
extra : convert_revision : c891435a31e81fb8294484aedf340c0c96c8afa2
2007-03-03 03:34:53 +00:00
Gabe Black
94133657a1 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : dcb1fc0c6252fb96a956640c6d7995679da725e5
2007-03-03 03:34:52 +00:00
Ali Saidi
4e8d2d1593 make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
    make ldtw(a) Twin 32 bit load work correctly

--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
2007-03-02 22:34:51 -05:00
Gabe Black
d8ada247f4 Forgot to commit this new file last earlier.
--HG--
extra : convert_revision : f2d80ae551b7e29426141d5c9fe355b43a0b9c7d
2007-03-02 14:43:27 +00:00
Gabe Black
ececf101c7 Make the m5 psuedo instructions use the BasicOperate format
--HG--
extra : convert_revision : f02da702ab9b99da124fac7e10a07386b04f3a0f
2007-02-28 16:49:17 +00:00
Gabe Black
eb57b4f214 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32

--HG--
extra : convert_revision : 88d1401f6e6b7c82344abef2c81b3c22bf6a0499
2007-02-28 16:39:42 +00:00
Gabe Black
29e5df890d Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.
--HG--
extra : convert_revision : ea873f01c62234c0542f310cc143c6a7c76ade94
2007-02-28 16:36:38 +00:00
Gabe Black
99948060b2 The "hostname" variable isn't used in the process classes. It should be removed from the other ones as well.
--HG--
extra : convert_revision : 0c07534de42d6c32ac26d9e43709111e3ab30d57
2007-02-28 16:29:25 +00:00
Gabe Black
dc8cc8de3d Fix issue with twolf where the presence or absence of two files, smred.sav or smred.sv2, would affect the outcome of the program. These names are based on the input file names which are in turn based on the input set selected. There may be more files like this generated for larger input sets, for example "mdred.sv3"
--HG--
extra : convert_revision : f4f1d3fd0fb28468b0ee507aaadf3c14aa9cf924
2007-02-27 10:37:48 +00:00
Gabe Black
a86ad3a512 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 7e8c3572ede7d93910fc3e2a2e76d9a38b1f4243
2007-02-26 10:34:45 +00:00
Ali Saidi
f892608ff7 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : a4f80ce975a23ba9858e6bf2dbbfed8897dd1810
2007-02-24 22:10:06 -05:00
Ali Saidi
cf0e202cba make m5 readfile work on solaris... we can have a solaris regression soon!
src/arch/sparc/isa/decoder.isa:
    add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
    fix O0-O5 operands registers
util/m5/Makefile.sparc:
    Make sparc makefile compile a 64bit binary
util/m5/m5.c:
    readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
    implement readfile and debugbreak

--HG--
extra : convert_revision : 139b3f480ee6342b37b5642e072c8486d91a3944
2007-02-24 22:05:01 -05:00
Gabe Black
c0c3a3f491 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : e0eb0240848698496bd55093a313eb2e0f512ebc
2007-02-23 12:54:07 +00:00
Gabe Black
6ae4cae971 Ali and I both made the same change and we only need it once. I liked mine a little better.
--HG--
extra : convert_revision : 3a1b7856e6143ca089fd6e36492608377dfede19
2007-02-23 01:05:34 +00:00
Gabe Black
187cc99e4e Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32

--HG--
extra : convert_revision : a7697ea8457a03318e3fcf34775bf3ecc4786e8a
2007-02-23 01:05:33 +00:00
Ali Saidi
a5b73a6e33 Merge zizzer:/bk/newmem
into  pb15.local:/Users/ali/work/m5.newmem

--HG--
extra : convert_revision : 887b278dac6db5ea17ade641de84d0ab8b05db96
2007-02-22 20:05:32 -05:00
Gabe Black
341a1eed6c Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32

--HG--
extra : convert_revision : 70dcd9d1d669c1c619411389487b7910861550e3
2007-02-22 13:18:23 +00:00
Gabe Black
34b4722aee Make the m5 pseudo instructions only work in FS. Also, make sure any undefined opcodes in impdep2 (which in SE is all of them) trap with an illegal_instruction exception.
--HG--
extra : convert_revision : dd7848d0685e4cc6f5fd5e3b846a3f70b62ee30a
2007-02-22 13:17:51 +00:00
Nathan Binkert
c003dda793 Make it easier to turn off the remote debugger
--HG--
extra : convert_revision : d88784736df5f9b498770fb7e98f52715669c0e1
2007-02-21 22:25:48 -08:00
Ali Saidi
b750d6a597 Merge zizzer:/bk/newmem
into  pb15.local:/Users/ali/work/m5.newmem

--HG--
extra : convert_revision : e0057583132ce545eb1867b446484e8984b97282
2007-02-22 01:15:16 -05:00
Nathan Binkert
fa4c3d74fe Get rid of the ConsoleListener SimObject and just fold the
relevant code directly into the SimConsole object.  Now,
you can easily turn off the listen port by just specifying
0 as the port.

--HG--
extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
2007-02-21 22:14:11 -08:00
Ali Saidi
63fef6b011 fix se compiling oops
--HG--
extra : convert_revision : ce7ac94da0ed6bad457a8a9e4c949b0c3b09c2ae
2007-02-22 01:11:04 -05:00
Nathan Binkert
783e642ed8 Make sure that all variables in the NSGigE device model are
initialized.

--HG--
extra : convert_revision : b4b156ed8e3c0c4c4f8043ff86dc232ebad38668
2007-02-21 20:45:05 -08:00
Nathan Binkert
8e77d771f9 Make comments refer to ticks not cycles
--HG--
extra : convert_revision : 4970a76890a3256073423a827dd0c55cfcb19a08
2007-02-21 20:35:30 -08:00
Ali Saidi
f01f8f1be6 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
2007-02-21 21:06:29 -05:00
Ali Saidi
7a2ecf9e26 add pseduo instruction support for sparc
util/m5/Makefile.alpha:
    Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
    Make the makefile more reasonable
util/m5/Makefile.alpha:
    Remove authors from copyright.
util/m5/Makefile.alpha:
    Updated Authors from bk prs info
util/m5/Makefile.alpha:
    bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
    Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
    Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
    split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
    ivle and ivlb aren't used anymore
util/m5/m5op.h:
    stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
    move the op ids into their own header file since we can share them between sparc and alpha

--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
2007-02-21 21:06:17 -05:00