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Merge zizzer.eecs.umich.edu:/bk/newmem

Browse source 
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : e0eb0240848698496bd55093a313eb2e0f512ebc
This commit is contained in:
Gabe Black 2007-02-23 12:54:07 +00:00
parent f8ffc84d0b a5b73a6e33
commit c0c3a3f491
25 changed files with 521 additions and 334 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
configs/common/FSConfig.py
View file

@ -78,7 +78,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
read_only = True))
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
self.sim_console = SimConsole()
self.kernel = binary('vmlinux')
self.pal = binary('ts_osfpal')
self.console = binary('console')

36
src/arch/alpha/isa/decoder.isa
View file

@ -790,19 +790,19 @@ decode OPCODE default Unknown::unknown() {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
AlphaPseudo::arm(xc->tcBase());
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
AlphaPseudo::quiesce(xc->tcBase());
PseudoInst::quiesce(xc->tcBase());
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
AlphaPseudo::quiesceNs(xc->tcBase(), R16);
PseudoInst::quiesceNs(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce);
0x03: quiesceCycles({{
AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
PseudoInst::quiesceCycles(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
0x04: quiesceTime({{
R0 = AlphaPseudo::quiesceTime(xc->tcBase());
R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
0x10: ivlb({{
warn_once("Obsolete M5 instruction ivlb encountered.\n");
@ -811,47 +811,47 @@ decode OPCODE default Unknown::unknown() {
warn_once("Obsolete M5 instruction ivlb encountered.\n");
}});
0x20: m5exit_old({{
AlphaPseudo::m5exit_old(xc->tcBase());
PseudoInst::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
AlphaPseudo::m5exit(xc->tcBase(), R16);
PseudoInst::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x31: loadsymbol({{
AlphaPseudo::loadsymbol(xc->tcBase());
PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
0x40: resetstats({{
AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
PseudoInst::dumpstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
AlphaPseudo::debugbreak(xc->tcBase());
PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
AlphaPseudo::switchcpu(xc->tcBase());
PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
PseudoInst::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, IsNonSpeculative);
0x55: m5anBegin({{
AlphaPseudo::anBegin(xc->tcBase(), R16);
PseudoInst::anBegin(xc->tcBase(), R16);
}}, IsNonSpeculative);
0x56: m5anWait({{
AlphaPseudo::anWait(xc->tcBase(), R16, R17);
PseudoInst::anWait(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
}
}

21
src/arch/alpha/tlb.cc
View file

@ -46,8 +46,7 @@
using namespace std;
using namespace EV5;
namespace AlphaISA
{
namespace AlphaISA {
///////////////////////////////////////////////////////////////////////
//
// Alpha TLB
@ -116,10 +115,11 @@ TLB::checkCacheability(RequestPtr &req)
#if ALPHA_TLASER
if (req->getPaddr() & PAddrUncachedBit39) {
if (req->getPaddr() & PAddrUncachedBit39)
#else
if (req->getPaddr() & PAddrUncachedBit43) {
if (req->getPaddr() & PAddrUncachedBit43)
#endif
{
// IPR memory space not implemented
if (PAddrIprSpace(req->getPaddr())) {
return new UnimpFault("IPR memory space not implemented!");
@ -313,10 +313,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER
if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->getVaddr()) == 2) {
VAddrSpaceEV5(req->getVaddr()) == 2)
#else
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
#endif
{
// only valid in kernel mode
if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
mode_kernel) {
@ -487,10 +488,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
// Check for "superpage" mapping
#if ALPHA_TLASER
if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->getVaddr()) == 2) {
VAddrSpaceEV5(req->getVaddr()) == 2)
#else
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
#endif
{
// only valid in kernel mode
if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
@ -592,6 +594,8 @@ TLB::index(bool advance)
return *pte;
}
/* end namespace AlphaISA */ }
DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
@ -633,4 +637,3 @@ CREATE_SIM_OBJECT(DTB)
}
REGISTER_SIM_OBJECT("AlphaDTB", DTB)
}

1
src/arch/sparc/isa/bitfields.isa
View file

@ -54,6 +54,7 @@ def bitfield FCN <29:25>;
def bitfield I <13>;
def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>;
def bitfield M5FUNC <15:7>;
def bitfield MMASK <3:0>;
def bitfield OP <31:30>;
def bitfield OP2 <24:22>;

16
src/arch/sparc/isa/decoder.isa
View file

@ -1009,7 +1009,20 @@ decode OP default Unknown::unknown()
0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
0x81: FailUnimpl::siam();
}
#if FULL_SYSTEM
// M5 special opcodes use the reserved IMPDEP2A opcode space
0x37: decode M5FUNC {
// we have 7 bits of space here to play with...
0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
}}, No_OpClass, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, No_OpClass, IsNonSpeculative);
}
#else
0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
#endif
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if(target & 0x3)
@ -1077,7 +1090,8 @@ decode OP default Unknown::unknown()
}
}}, IsSerializeAfter, IsNonSpeculative);
}
0x3B: Nop::flush({{/*Instruction memory flush*/}});
0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
MemWriteOp);
0x3C: save({{
if(Cansave == 0)
{

4
src/arch/sparc/isa/includes.isa
View file

@ -70,6 +70,10 @@ output exec {{
#include <ieeefp.h>
#endif
#if FULL_SYSTEM
#include "sim/pseudo_inst.hh"
#endif
#include <limits>
#include <cmath>

6
src/arch/sparc/isa/operands.isa
View file

@ -100,6 +100,12 @@ def operands {{
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9),
'O0': ('IntReg', 'udw', '24', 'IsInteger', 10),
'O1': ('IntReg', 'udw', '25', 'IsInteger', 11),
'O2': ('IntReg', 'udw', '26', 'IsInteger', 12),
'O3': ('IntReg', 'udw', '27', 'IsInteger', 13),
'O4': ('IntReg', 'udw', '28', 'IsInteger', 14),
'O5': ('IntReg', 'udw', '29', 'IsInteger', 15),
# Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),

54
src/arch/sparc/tlb.cc
View file

@ -43,8 +43,7 @@
/* @todo remove some of the magic constants. -- ali
* */
namespace SparcISA
{
namespace SparcISA {
TLB::TLB(const std::string &name, int s)
: SimObject(name), size(s), usedEntries(0), lastReplaced(0),
@ -596,21 +595,36 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
// Be fast if we can!
if (cacheValid && cacheState == tlbdata) {
if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
(!write || cacheEntry[0]->pte.writable())) {
req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
vaddr & cacheEntry[0]->pte.size()-1 );
return NoFault;
}
if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
(!write || cacheEntry[1]->pte.writable())) {
req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
vaddr & cacheEntry[1]->pte.size()-1 );
return NoFault;
}
}
if (cacheEntry[0]) {
TlbEntry *ce = cacheEntry[0];
Addr ce_va = ce->range.va;
if (cacheAsi[0] == asi &&
ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
(!write || ce->pte.writable())) {
req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
req->setFlags(req->getFlags() | UNCACHEABLE);
DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
return NoFault;
} // if matched
} // if cache entry valid
if (cacheEntry[1]) {
TlbEntry *ce = cacheEntry[1];
Addr ce_va = ce->range.va;
if (cacheAsi[1] == asi &&
ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
(!write || ce->pte.writable())) {
req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
req->setFlags(req->getFlags() | UNCACHEABLE);
DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
return NoFault;
} // if matched
} // if cache entry valid
}
bool red = bits(tlbdata,1,1);
bool priv = bits(tlbdata,2,2);
@ -756,7 +770,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
}
if (e->pte.sideffect())
if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
req->setFlags(req->getFlags() | UNCACHEABLE);
// cache translation date for next translation
@ -1329,6 +1343,9 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
}
}
/* end namespace SparcISA */ }
using namespace SparcISA;
DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
@ -1371,4 +1388,3 @@ CREATE_SIM_OBJECT(DTB)
}
REGISTER_SIM_OBJECT("SparcDTB", DTB)
}

18
src/base/statistics.hh
View file

@ -70,7 +70,7 @@
class Callback;
/** The current simulated cycle. */
/** The current simulated tick. */
extern Tick curTick;
/* A namespace for all of the Statistics */
@ -598,9 +598,9 @@ struct StatStor
};
/**
* Templatized storage and interface to a per-cycle average stat. This keeps
* a current count and updates a total (count * cycles) when this count
* changes. This allows the quick calculation of a per cycle count of the item
* Templatized storage and interface to a per-tick average stat. This keeps
* a current count and updates a total (count * ticks) when this count
* changes. This allows the quick calculation of a per tick count of the item
* being watched. This is good for keeping track of residencies in structures
* among other things.
*/
@ -613,9 +613,9 @@ struct AvgStor
private:
/** The current count. */
Counter current;
/** The total count for all cycles. */
/** The total count for all tick. */
mutable Result total;
/** The cycle that current last changed. */
/** The tick that current last changed. */
mutable Tick last;
public:
@ -1563,7 +1563,7 @@ struct FancyStor
};
/**
* Templatized storage for distribution that calculates per cycle mean and
* Templatized storage for distribution that calculates per tick mean and
* variance.
*/
struct AvgFancy
@ -2280,7 +2280,7 @@ class Value : public Wrap<Value, ValueBase, ScalarStatData>
};
/**
* A stat that calculates the per cycle average of a value.
* A stat that calculates the per tick average of a value.
* @sa Stat, ScalarBase, AvgStor
*/
template<int N = 0>
@ -2417,7 +2417,7 @@ class StandardDeviation
};
/**
* Calculates the per cycle mean and variance of the samples.
* Calculates the per tick mean and variance of the samples.
* @sa Stat, DistBase, AvgFancy
*/
template<int N = 0>

26
src/dev/ns_gige.cc
View file

@ -92,28 +92,30 @@ NSGigE::NSGigE(Params *p)
: PciDev(p), ioEnable(false),
txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
txXferLen(0), rxXferLen(0), clock(p->clock),
txState(txIdle), txEnable(false), CTDD(false),
txXferLen(0), rxXferLen(0), rxDmaFree(false), txDmaFree(false),
clock(p->clock),
txState(txIdle), txEnable(false), CTDD(false), txHalt(false),
txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
rxEnable(false), CRDD(false), rxPktBytes(0),
rxEnable(false), CRDD(false), rxPktBytes(0), rxHalt(false),
rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false),
eepromState(eepromStart), rxDmaReadEvent(this), rxDmaWriteEvent(this),
eepromState(eepromStart), eepromClk(false), eepromBitsToRx(0),
eepromOpcode(0), eepromAddress(0), eepromData(0),
dmaReadDelay(p->dma_read_delay), dmaWriteDelay(p->dma_write_delay),
dmaReadFactor(p->dma_read_factor), dmaWriteFactor(p->dma_write_factor),
rxDmaData(NULL), rxDmaAddr(0), rxDmaLen(0),
txDmaData(NULL), txDmaAddr(0), txDmaLen(0),
rxDmaReadEvent(this), rxDmaWriteEvent(this),
txDmaReadEvent(this), txDmaWriteEvent(this),
dmaDescFree(p->dma_desc_free), dmaDataFree(p->dma_data_free),
txDelay(p->tx_delay), rxDelay(p->rx_delay),
rxKickTick(0), rxKickEvent(this), txKickTick(0), txKickEvent(this),
txEvent(this), rxFilterEnable(p->rx_filter), acceptBroadcast(false),
acceptMulticast(false), acceptUnicast(false),
txEvent(this), rxFilterEnable(p->rx_filter),
acceptBroadcast(false), acceptMulticast(false), acceptUnicast(false),
acceptPerfect(false), acceptArp(false), multicastHashEnable(false),
intrTick(0), cpuPendingIntr(false),
intrDelay(p->intr_delay), intrTick(0), cpuPendingIntr(false),
intrEvent(0), interface(0)
{
intrDelay = p->intr_delay;
dmaReadDelay = p->dma_read_delay;
dmaWriteDelay = p->dma_write_delay;
dmaReadFactor = p->dma_read_factor;
dmaWriteFactor = p->dma_write_factor;
regsReset();
memcpy(&rom.perfectMatch, p->eaddr.bytes(), ETH_ADDR_LEN);

237
src/dev/simconsole.cc
View file

@ -56,17 +56,31 @@
using namespace std;
////////////////////////////////////////////////////////////////////////
//
//
SimConsole::Event::Event(SimConsole *c, int fd, int e)
/*
* Poll event for the listen socket
*/
SimConsole::ListenEvent::ListenEvent(SimConsole *c, int fd, int e)
: PollEvent(fd, e), cons(c)
{
}
void
SimConsole::Event::process(int revent)
SimConsole::ListenEvent::process(int revent)
{
cons->accept();
}
/*
* Poll event for the data socket
*/
SimConsole::DataEvent::DataEvent(SimConsole *c, int fd, int e)
: PollEvent(fd, e), cons(c)
{
}
void
SimConsole::DataEvent::process(int revent)
{
if (revent & POLLIN)
cons->data();
@ -74,41 +88,76 @@ SimConsole::Event::process(int revent)
cons->detach();
}
SimConsole::SimConsole(const string &name, ostream *os, int num)
: SimObject(name), event(NULL), number(num), in_fd(-1), out_fd(-1),
listener(NULL), txbuf(16384), rxbuf(16384), outfile(os)
/*
* SimConsole code
*/
SimConsole::SimConsole(const string &name, ostream *os, int num, int port)
: SimObject(name), listenEvent(NULL), dataEvent(NULL), number(num),
data_fd(-1), txbuf(16384), rxbuf(16384), outfile(os)
#if TRACING_ON == 1
, linebuf(16384)
#endif
{
if (outfile)
outfile->setf(ios::unitbuf);
if (port)
listen(port);
}
SimConsole::~SimConsole()
{
close();
if (data_fd != -1)
::close(data_fd);
if (listenEvent)
delete listenEvent;
if (dataEvent)
delete dataEvent;
}
///////////////////////////////////////////////////////////////////////
// socket creation and console attach
//
void
SimConsole::listen(int port)
{
while (!listener.listen(port, true)) {
DPRINTF(Console,
": can't bind address console port %d inuse PID %d\n",
port, getpid());
port++;
}
int p1, p2;
p2 = name().rfind('.') - 1;
p1 = name().rfind('.', p2);
ccprintf(cerr, "Listening for %s connection on port %d\n",
name().substr(p1+1,p2-p1), port);
listenEvent = new ListenEvent(this, listener.getfd(), POLLIN);
pollQueue.schedule(listenEvent);
}
void
SimConsole::close()
SimConsole::accept()
{
if (in_fd != -1)
::close(in_fd);
if (!listener.islistening())
panic("%s: cannot accept a connection if not listening!", name());
if (out_fd != in_fd && out_fd != -1)
::close(out_fd);
}
int fd = listener.accept(true);
if (data_fd != -1) {
char message[] = "console already attached!\n";
::write(fd, message, sizeof(message));
::close(fd);
return;
}
void
SimConsole::attach(int in, int out, ConsoleListener *l)
{
in_fd = in;
out_fd = out;
listener = l;
event = new Event(this, in, POLLIN);
pollQueue.schedule(event);
data_fd = fd;
dataEvent = new DataEvent(this, data_fd, POLLIN);
pollQueue.schedule(dataEvent);
stringstream stream;
ccprintf(stream, "==== m5 slave console: Console %d ====", number);
@ -119,26 +168,23 @@ SimConsole::attach(int in, int out, ConsoleListener *l)
write((const uint8_t *)stream.str().c_str(), stream.str().size());
DPRINTFN("attach console %d\n", number);
txbuf.readall(out);
txbuf.readall(data_fd);
}
void
SimConsole::detach()
{
close();
in_fd = -1;
out_fd = -1;
pollQueue.remove(event);
if (listener) {
listener->add(this);
listener = NULL;
if (data_fd != -1) {
::close(data_fd);
data_fd = -1;
}
pollQueue.remove(dataEvent);
delete dataEvent;
dataEvent = NULL;
DPRINTFN("detach console %d\n", number);
}
@ -159,12 +205,12 @@ SimConsole::data()
size_t
SimConsole::read(uint8_t *buf, size_t len)
{
if (in_fd < 0)
if (data_fd < 0)
panic("Console not properly attached.\n");
size_t ret;
do {
ret = ::read(in_fd, buf, len);
ret = ::read(data_fd, buf, len);
} while (ret == -1 && errno == EINTR);
@ -183,12 +229,12 @@ SimConsole::read(uint8_t *buf, size_t len)
size_t
SimConsole::write(const uint8_t *buf, size_t len)
{
if (out_fd < 0)
if (data_fd < 0)
panic("Console not properly attached.\n");
size_t ret;
for (;;) {
ret = ::write(out_fd, buf, len);
ret = ::write(data_fd, buf, len);
if (ret >= 0)
break;
@ -268,7 +314,7 @@ SimConsole::out(char c)
txbuf.write(c);
if (out_fd >= 0)
if (data_fd >= 0)
write(c);
if (outfile)
@ -279,23 +325,11 @@ SimConsole::out(char c)
}
void
SimConsole::serialize(ostream &os)
{
}
void
SimConsole::unserialize(Checkpoint *cp, const std::string &section)
{
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
SimObjectParam<ConsoleListener *> listener;
SimObjectParam<IntrControl *> intr_control;
Param<string> output;
Param<int> port;
Param<bool> append_name;
Param<int> number;
@ -303,9 +337,9 @@ END_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
INIT_PARAM(listener, "console listener"),
INIT_PARAM(intr_control, "interrupt controller"),
INIT_PARAM(output, "file to dump output to"),
INIT_PARAM(port, ""),
INIT_PARAM_DFLT(append_name, "append name() to filename", true),
INIT_PARAM_DFLT(number, "console number", 0)
@ -322,100 +356,7 @@ CREATE_SIM_OBJECT(SimConsole)
stream = simout.find(filename);
}
SimConsole *console = new SimConsole(getInstanceName(), stream, number);
((ConsoleListener *)listener)->add(console);
return console;
return new SimConsole(getInstanceName(), stream, number, port);
}
REGISTER_SIM_OBJECT("SimConsole", SimConsole)
////////////////////////////////////////////////////////////////////////
//
//
ConsoleListener::ConsoleListener(const string &name)
: SimObject(name), event(NULL)
{}
ConsoleListener::~ConsoleListener()
{
if (event)
delete event;
}
void
ConsoleListener::Event::process(int revent)
{
listener->accept();
}
///////////////////////////////////////////////////////////////////////
// socket creation and console attach
//
void
ConsoleListener::listen(int port)
{
while (!listener.listen(port, true)) {
DPRINTF(Console,
": can't bind address console port %d inuse PID %d\n",
port, getpid());
port++;
}
int p1, p2;
p2 = name().rfind('.') - 1;
p1 = name().rfind('.', p2);
ccprintf(cerr, "Listening for %s connection on port %d\n",
name().substr(p1+1,p2-p1), port);
event = new Event(this, listener.getfd(), POLLIN);
pollQueue.schedule(event);
}
void
ConsoleListener::add(SimConsole *cons)
{ ConsoleList.push_back(cons);}
void
ConsoleListener::accept()
{
if (!listener.islistening())
panic("%s: cannot accept a connection if not listening!", name());
int sfd = listener.accept(true);
if (sfd != -1) {
iter_t i = ConsoleList.begin();
iter_t end = ConsoleList.end();
if (i == end) {
close(sfd);
} else {
(*i)->attach(sfd, this);
i = ConsoleList.erase(i);
}
}
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener)
Param<int> port;
END_DECLARE_SIM_OBJECT_PARAMS(ConsoleListener)
BEGIN_INIT_SIM_OBJECT_PARAMS(ConsoleListener)
INIT_PARAM_DFLT(port, "listen port", 3456)
END_INIT_SIM_OBJECT_PARAMS(ConsoleListener)
CREATE_SIM_OBJECT(ConsoleListener)
{
ConsoleListener *listener = new ConsoleListener(getInstanceName());
listener->listen(port);
return listener;
}
REGISTER_SIM_OBJECT("ConsoleListener", ConsoleListener)

76
src/dev/simconsole.hh
View file

@ -53,29 +53,46 @@ class SimConsole : public SimObject
Uart *uart;
protected:
class Event : public PollEvent
class ListenEvent : public PollEvent
{
protected:
SimConsole *cons;
public:
Event(SimConsole *c, int fd, int e);
ListenEvent(SimConsole *c, int fd, int e);
void process(int revent);
};
friend class Event;
Event *event;
friend class ListenEvent;
ListenEvent *listenEvent;
class DataEvent : public PollEvent
{
protected:
SimConsole *cons;
public:
DataEvent(SimConsole *c, int fd, int e);
void process(int revent);
};
friend class DataEvent;
DataEvent *dataEvent;
protected:
int number;
int in_fd;
int out_fd;
ConsoleListener *listener;
int data_fd;
public:
SimConsole(const std::string &name, std::ostream *os, int num);
SimConsole(const std::string &name, std::ostream *os, int num, int port);
~SimConsole();
protected:
ListenSocket listener;
void listen(int port);
void accept();
protected:
CircleBuf txbuf;
CircleBuf rxbuf;
@ -88,17 +105,13 @@ class SimConsole : public SimObject
///////////////////////
// Terminal Interface
void attach(int fd, ConsoleListener *l = NULL) { attach(fd, fd, l); }
void attach(int in, int out, ConsoleListener *l = NULL);
void detach();
void data();
void close();
void read(uint8_t &c) { read(&c, 1); }
size_t read(uint8_t *buf, size_t len);
void write(uint8_t c) { write(&c, 1); }
size_t write(const uint8_t *buf, size_t len);
void detach();
public:
/////////////////
@ -126,43 +139,6 @@ class SimConsole : public SimObject
//Ask the console if data is available
bool dataAvailable() { return !rxbuf.empty(); }
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
class ConsoleListener : public SimObject
{
protected:
class Event : public PollEvent
{
protected:
ConsoleListener *listener;
public:
Event(ConsoleListener *l, int fd, int e)
: PollEvent(fd, e), listener(l) {}
void process(int revent);
};
friend class Event;
Event *event;
typedef std::list<SimConsole *> list_t;
typedef list_t::iterator iter_t;
list_t ConsoleList;
protected:
ListenSocket listener;
public:
ConsoleListener(const std::string &name);
~ConsoleListener();
void add(SimConsole *cons);
void accept();
void listen(int port);
};
#endif // __CONSOLE_HH__

2
src/python/m5/main.py
View file

@ -297,7 +297,7 @@ def main():
internal.trace.cvar.enabled = True
internal.event.create(enable_trace, int(options.trace_start))
else:
internal.trace.enabled = True
internal.trace.cvar.enabled = True
internal.trace.output(options.trace_file)

5
src/python/m5/objects/SimConsole.py
View file

@ -1,14 +1,11 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class ConsoleListener(SimObject):
type = 'ConsoleListener'
port = Param.TcpPort(3456, "listen port")
class SimConsole(SimObject):
type = 'SimConsole'
append_name = Param.Bool(True, "append name() to filename")
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
listener = Param.ConsoleListener("console listener")
port = Param.TcpPort(3456, "listen port")
number = Param.Int(0, "console number")
output = Param.String('console', "file to dump output to")

6
src/python/m5/objects/T1000.py
View file

@ -3,7 +3,7 @@ from m5.proxy import *
from Device import BasicPioDevice, IsaFake, BadAddr
from Uart import Uart8250
from Platform import Platform
from SimConsole import SimConsole, ConsoleListener
from SimConsole import SimConsole
class MmDisk(BasicPioDevice):
@ -69,11 +69,11 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
hconsole = SimConsole(listener = ConsoleListener())
hconsole = SimConsole()
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
pconsole = SimConsole(listener = ConsoleListener())
pconsole = SimConsole()
puart0 = Uart8250(pio_addr=0x1f10000000)
# Attach I/O devices to specified bus object. Can't do this

2
src/sim/pseudo_inst.cc
View file

@ -55,7 +55,7 @@ using namespace std;
using namespace Stats;
using namespace TheISA;
namespace AlphaPseudo
namespace PseudoInst
{
void
arm(ThreadContext *tc)

2
src/sim/pseudo_inst.hh
View file

@ -33,7 +33,7 @@ class ThreadContext;
//We need the "Tick" and "Addr" data types from here
#include "sim/host.hh"
namespace AlphaPseudo
namespace PseudoInst
{
/**
* @todo these externs are only here for a hack in fullCPU::takeOver...

36
src/sim/system.cc
View file

@ -142,6 +142,7 @@ System::~System()
}
int rgdb_wait = -1;
int rgdb_enable = true;
void
System::setMemoryMode(MemoryMode mode)
@ -152,7 +153,9 @@ System::setMemoryMode(MemoryMode mode)
bool System::breakpoint()
{
return remoteGDB[0]->breakpoint();
if (remoteGDB.size())
return remoteGDB[0]->breakpoint();
return false;
}
int
@ -174,22 +177,24 @@ System::registerThreadContext(ThreadContext *tc, int id)
threadContexts[id] = tc;
numcpus++;
RemoteGDB *rgdb = new RemoteGDB(this, tc);
GDBListener *gdbl = new GDBListener(rgdb, 7000 + id);
gdbl->listen();
/**
* Uncommenting this line waits for a remote debugger to connect
* to the simulator before continuing.
*/
if (rgdb_wait != -1 && rgdb_wait == id)
gdbl->accept();
if (rgdb_enable) {
RemoteGDB *rgdb = new RemoteGDB(this, tc);
GDBListener *gdbl = new GDBListener(rgdb, 7000 + id);
gdbl->listen();
/**
* Uncommenting this line waits for a remote debugger to
* connect to the simulator before continuing.
*/
if (rgdb_wait != -1 && rgdb_wait == id)
gdbl->accept();
if (remoteGDB.size() <= id) {
remoteGDB.resize(id + 1);
if (remoteGDB.size() <= id) {
remoteGDB.resize(id + 1);
}
remoteGDB[id] = rgdb;
}
remoteGDB[id] = rgdb;
return id;
}
@ -210,7 +215,8 @@ System::replaceThreadContext(ThreadContext *tc, int id)
}
threadContexts[id] = tc;
remoteGDB[id]->replaceThreadContext(tc);
if (id < remoteGDB.size())
remoteGDB[id]->replaceThreadContext(tc);
}
#if !FULL_SYSTEM

2
util/m5/Makefile → util/m5/Makefile.alpha
View file

@ -36,7 +36,7 @@ AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
CFLAGS=-O2
OBJS=m5.o m5op.o
OBJS=m5.o m5op_alpha.o
all: m5

53
util/m5/Makefile.sparc Normal file
View file

@ -0,0 +1,53 @@
# Copyright (c) 2005-2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
# Ali Saidi
### If we are not compiling on an alpha, we must use cross tools ###
ifneq ($(shell uname -m), sun4v)
CROSS_COMPILE?=sparc64-sun-solaris2.10-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
CFLAGS=-O2
OBJS=m5.o m5op_sparc.o
all: m5
%.o: %.S
$(CC) $(CFLAGS) -o $@ -c $<
%.o: %.c
$(CC) $(CFLAGS) -o $@ -c $<
m5: $(OBJS)
$(CC) -o $@ $(OBJS)
clean:
rm -f *.o m5

19
util/m5/m5.c
View file

@ -70,24 +70,6 @@ main(int argc, char *argv[])
command = argv[1];
if (COMPARE("ivlb")) {
if (argc != 3)
usage();
arg1 = strtoul(argv[2], NULL, 0);
m5_ivlb(arg1);
return 0;
}
if (COMPARE("ivle")) {
if (argc != 3)
usage();
arg1 = strtoul(argv[2], NULL, 0);
m5_ivle(arg1);
return 0;
}
if (COMPARE("initparam")) {
if (argc != 2)
usage();
@ -203,6 +185,7 @@ main(int argc, char *argv[])
if (COMPARE("loadsymbol")) {
m5_loadsymbol(arg1);
return 0;
}
if (COMPARE("readfile")) {
char buf[256*1024];
int offset = 0;

2
util/m5/m5op.h
View file

@ -32,7 +32,7 @@
#ifndef __M5OP_H__
#define __M5OP_H__
#include <asm/types.h>
#include <stdint.h>
void arm(uint64_t address);
void quiesce(void);

23
util/m5/m5op.S → util/m5/m5op_alpha.S
View file

@ -31,28 +31,7 @@
#define m5_op 0x01
#define arm_func 0x00
#define quiesce_func 0x01
#define quiescens_func 0x02
#define quiescecycle_func 0x03
#define quiescetime_func 0x04
#define ivlb 0x10 // obsolete
#define ivle 0x11 // obsolete
#define exit_old_func 0x20 // deprecated!
#define exit_func 0x21
#define initparam_func 0x30
#define loadsymbol_func 0x31
#define resetstats_func 0x40
#define dumpstats_func 0x41
#define dumprststats_func 0x42
#define ckpt_func 0x43
#define readfile_func 0x50
#define debugbreak_func 0x51
#define switchcpu_func 0x52
#define addsymbol_func 0x53
#define panic_func 0x54
#define anbegin_func 0x55
#define anwait_func 0x56
#include "m5ops.h"
#define INST(op, ra, rb, func) \
.long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))

152
util/m5/m5op_sparc.S Normal file
View file

@ -0,0 +1,152 @@
/*
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Ali Saidi
*/
#define m5_op 0x2
#define m5_op3 0x37
#include "m5ops.h"
#define INST(func, rs1, rs2, rd) \
.long (m5_op) << 30 | (rd) << 25 | (m5_op3) << 19 | (func) << 7 | \
(rs1) << 14 | (rs2) << 0;
#define LEAF(func) \
.section ".text"; \
.align 4; \
.global func; \
.type func, #function; \
func:
#define END(func) \
.size func, (.-func)
#define M5EXIT INST(exit_func, 0, 0, 0)
#define PANIC INST(panic_func, 0, 0, 0)
LEAF(m5_exit)
retl
M5EXIT
END(m5_exit)
LEAF(m5_panic)
retl
PANIC
END(m5_panic)
/* !!!!!! All code below here just panics !!!!!! */
LEAF(arm)
retl
PANIC
END(arm)
LEAF(quiesce)
retl
PANIC
END(quiesce)
LEAF(quiesceNs)
retl
PANIC
END(quiesceNs)
LEAF(quiesceCycle)
retl
PANIC
END(quiesceCycle)
LEAF(quiesceTime)
retl
PANIC
END(quiesceTime)
LEAF(m5_initparam)
retl
PANIC
END(m5_initparam)
LEAF(m5_loadsymbol)
retl
PANIC
END(m5_loadsymbol)
LEAF(m5_reset_stats)
retl
PANIC
END(m5_reset_stats)
LEAF(m5_dump_stats)
retl
PANIC
END(m5_dump_stats)
LEAF(m5_dumpreset_stats)
retl
PANIC
END(m5_dumpreset_stats)
LEAF(m5_checkpoint)
retl
PANIC
END(m5_checkpoint)
LEAF(m5_readfile)
retl
PANIC
END(m5_readfile)
LEAF(m5_debugbreak)
retl
PANIC
END(m5_debugbreak)
LEAF(m5_switchcpu)
retl
PANIC
END(m5_switchcpu)
LEAF(m5_addsymbol)
retl
PANIC
END(m5_addsymbol)
LEAF(m5_anbegin)
retl
PANIC
END(m5_anbegin)
LEAF(m5_anwait)
retl
PANIC
END(m5_anwait)

54
util/m5/m5ops.h Normal file
View file

@ -0,0 +1,54 @@
/*
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Ali Saidi
*/
#define arm_func 0x00
#define quiesce_func 0x01
#define quiescens_func 0x02
#define quiescecycle_func 0x03
#define quiescetime_func 0x04
#define ivlb 0x10 // obsolete
#define ivle 0x11 // obsolete
#define exit_old_func 0x20 // deprecated!
#define exit_func 0x21
#define initparam_func 0x30
#define loadsymbol_func 0x31
#define resetstats_func 0x40
#define dumpstats_func 0x41
#define dumprststats_func 0x42
#define ckpt_func 0x43
#define readfile_func 0x50
#define debugbreak_func 0x51
#define switchcpu_func 0x52
#define addsymbol_func 0x53
#define panic_func 0x54
#define anbegin_func 0x55
#define anwait_func 0x56