use quiesceNs on other CPUs
panic rather than spin on an error
console/Makefile:
Add m5op to the build process
console/dbmentry.S:
use quiesceNs on other CPUs
console/printf.c:
panic rather than spin on an error.
console/console.c:
the go parameter to unixBoot is never used, so get rid of it.
just panic if we return from unixBoot since it's never supposed
to happen.
remove the MAX_CPUS parameter and the bootStrapImpure variable
and just allocate memory as needed. (Can in theory support many
more CPUs.)
only compile one console
console/Makefile:
Now that the location of the m5 backdoor is passed into the
console via the m5AlphaAccess variable, we only need to
compile one console, and don't need to define TLASER or TSUNAMI
console/console.c:
Don't hardcode the location of the AlphaAccess structure, but
rely on m5 to pass in the correct value.
Setup "volatile struct AlphaAccess *m5AlphaAccess" for use and
get rid of the hardcoded usage.
I steped on while doing it
console/console.c:
Allocate more HWRPB pages so we have room for 64 percpu_rpbs
Fix writing of Console Relocation Block virtual addresses so that
if they are outside of the first page, which they will be with more
than 8 processors, the correct adress is written
palcode/Makefile:
Update makefile for tsunami with 64 processors
palcode/platform_m5.S:
Add support for tsunami with 64 processors
console/console.c:
Remove Printed SimOS references and replace with M5
Rework the SMP stuff, so we don't trash any stacks, or what we
thought were stacks, but are actually other ppls memory.
console/dbmentry.s:
add a carefully crafted piece of assembly that doesn't use the stack,
so we don't clobber anthing in the time between when we are spinning
and when the OS tells us to go.
palcode/platform_m5.s:
add/fix code for IPI, multiprocessor interrupts (DIR), and initial
bootstrapping of the cpu
addresses so the uncachable bit is set for tsunami.
console/Makefile:
console/console.c:
changed to generate tlaser and tsunami console code at different addresses
measure. The rest of the registers I used are touched by the tlaser
platform code so I would guess their are fair game.
Random memory troubles hopefully over.
console/Makefile:
palcode/Makefile:
moved header files to /h so updated make file for that
console/dbmentry.s:
console/paljtokern.s:
console/paljtoslave.s:
upadated to use osf file that the palcode uses, one less file
console/Makefile:
Updated to build on linux and removed
lots of crud that compiled, disassembled, and then reassembled
console/dbmentry.s:
the assembler didn't like they comments, so I removed them
console/printf.c:
Gcc was very unhappy, so I fixed this line
h/lib.h:
time_t is defined in a std header, and this was causing some problems
deleted and then upon realizing we needed them undeleted a bunch of
header files in the palcode dir
console/Makefile:
fixed so it will work with tru64... still haven't got the console to build under linux
palcode/platform_m5.s:
fixed code to "fake" srm console interrupt handling correctly
include serial interrupts
console/console.c:
0 the system type, let m5 overwrite
palcode/platform_m5.s:
add some comments and make the timer interrupt actually care what CPU it happened on
makefile to that end. Additionally made a change in console to
preserve t7 on call back because linux uses it for the "current"
pointer.
console/Makefile:
Changed makefile back to using gcc and gas rather then trying to
cross-compile for now
console/console.c:
Put code in to save t7 on CallBackFixup() call and changed the
system type to Tsunami
palcode/Makefile:
updated palcode makefile to have targets for tlaser and tsunami
