Commit graph

9707 commits

Author SHA1 Message Date
Andreas Hansson
cc8911261e util: Auto generate the packet proto definitions
This patch simplifies the usage of the packet trace encoder/decoder by
attempting to automatically generating the packet proto definitions in
case they cannot be found.
2013-05-30 12:53:53 -04:00
Andreas Hansson
4c7a283e55 base: Avoid size limitation on protobuf coded streams
This patch changes how the streams are created to avoid the size
limitation on the coded streams. As we only read/write a single
message at a time, there is never any message larger than a few
bytes. However, the coded stream eventually complains that its
internal counter reaches 64+ MByte if the total file size exceeds this
value.

Based on suggestions in the protobuf discussion forums, the coded
stream is now created for every message that is read/written. The
result is that the internal byte count never goes about tens of bytes,
and we can read/write any size file that the underlying file I/O can
handle.
2013-05-30 12:53:53 -04:00
Andreas Hansson
d1a43d83da cpu: Make hash struct instead of class to please clang
This patch changes the type of the hash function for BasicBlockRanges
to match the original definition of the templatized type. Without
this, clang raises a warning and combined with the "-Werror" flag this
causes compilation to fail.
2013-05-30 12:53:52 -04:00
Malek Musleh
64af621cc6 ruby: slicc: fix error msg in TypeFieldMemberAST.py 2013-05-21 11:57:14 -05:00
Nilay Vaish
af2e83c7f1 x86, regressions: updates stats
This is due to op class, function call, walker patches.
2013-05-21 11:41:27 -05:00
Gedare Bloom
22b60c57e6 x86: Squash outstanding walks when instructions are squashed.
This is the x86 version of the ARM changeset baa17ba80e06. In case an
instruction has been squashed by the o3 cpu, this patch allows page
table walker to avoid carrying out a pending translation that the
instruction requested for.
2013-05-21 11:40:11 -05:00
Nilay Vaish
30fe807316 x86: mark instructions for being function call/return
Currently call and return instructions are marked as IsCall and IsReturn. Thus, the
branch predictor does not use RAS for these instructions. Similarly, the number of
function calls that took place is recorded as 0. This patch marks these instructions
as they should be.
2013-05-21 11:34:41 -05:00
Nilay Vaish
fba40864aa x86: add op class for int and fp microops in isa description
Currently all the integer microops are marked as IntAluOp and the floating
point microops are marked as FloatAddOp. This patch adds support for marking
different microops differently. Now IntMultOp, IntDivOp, FloatDivOp,
FloatMultOp, FloatCvtOp, FloatSqrtOp classes will be used as well. This will
help in providing different latencies for different op class.
2013-05-21 11:33:57 -05:00
Nilay Vaish
5b49c3d255 stats: updates statistics for ruby regressions 2013-05-21 11:32:57 -05:00
Nilay Vaish
4ef466cc8a ruby: moesi hammer: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:45 -05:00
Nilay Vaish
09d5bc7e6f ruby: mesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:38 -05:00
Nilay Vaish
bd3d1955da ruby: moesi cmp token: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:24 -05:00
Nilay Vaish
e7ce518168 ruby: moesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:15 -05:00
Nilay Vaish
9bc75e3c58 configs: ruby: pass the option use_map to directory controller
The option was not being passed to directory controllers for the protocols
MOESI_CMP_token and MOESI_CMP_directory. This was resulting in an error
while instantiating the directory controller as it tries to access the
wrong type of memory.
2013-05-21 11:32:08 -05:00
Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
59a7abff29 ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby.

As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines different
functions for accessing the CacheProfiler. These functions are then invoked
in the .sm files. I find this approach opaque and prone to error. Secondly,
we probably should not be paying the cost of a function call for recording
statistics.

Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would happen
in place, so no function calls. The patch also removes the CacheProfiler class.

--HG--
rename : src/mem/slicc/ast/InfixOperatorExprAST.py => src/mem/slicc/ast/OperatorExprAST.py
2013-05-21 11:31:31 -05:00
Anthony Gutierrez
d3c33d91b6 cpu: remove local/globalHistoryBits params from branch pred
having separate params for the local/globalHistoryBits and the
local/globalPredictorSize can lead to inconsistencies if they
are not carefully set. this patch dervies the number of bits
necessary to index into the local/global predictors based on
their size.

the value of the localHistoryTableSize for the ARM O3 CPU has been
increased to 1024 from 64, which is more accurate for an A15 based
on some correlation against A15 hardware.
2013-05-14 18:39:47 -04:00
Andreas Sandberg
4e52789c6d kvm: Add support for disabling coalesced MMIO
Add the option useCoalescedMMIO to the BaseKvmCPU. The default
behavior is to disable coalesced MMIO since this hasn't been heavily
tested.
2013-05-14 16:02:45 +02:00
Andreas Sandberg
3ba93822cc kvm: Dump state before panic in KVM exit handlers 2013-05-14 15:59:43 +02:00
Andreas Sandberg
98483ba858 kvm: Fix the memory interface used by KVM
The CpuPort class was removed before the KVM patches were committed,
which means that the KVM interface currently doesn't compile. This
changeset adds the BaseKvmCPU::KVMCpuPort class which derives from
MasterPort. This class is used on the data and instruction ports
instead of the old CpuPort.
2013-05-14 15:56:04 +02:00
Andreas Sandberg
1ae30c68c1 arm: Add support for the m5fail pseudo-op 2013-05-14 15:06:50 +02:00
Andreas Sandberg
e1cbe33c72 arm: Fix compilation error in m5 utility
Changeset 5ca6098b9560 accidentally broke the m5 utility. This
changeset adds the missing co-processor call used to trigger the
pseudo-op in ARM mode and fixes an alignment issue that caused some
pseudo-ops to leave thumb mode.
2013-05-14 15:03:45 +02:00
Andreas Sandberg
4153a76478 arm: Make libm5 a dependency of the m5 utility
The m5 utility wasn't relinked properly since libm5.a wasn't a
dependency of the utility. This changeset addresses that issue.
2013-05-07 14:47:04 +02:00
Andreas Sandberg
e316e4e5fe kvm: Add a stat counting number of instructions executed
This changeset adds a 'numInsts' stat to the KVM-based CPU. It also
cleans up the variable names in kvmRun to make the distinction between
host cycles and estimated simulated cycles clearer. As a bonus
feature, it also fixes a warning (unreferenced variable) when
compiling in fast mode.
2013-05-02 12:03:43 +02:00
Andreas Sandberg
fa249461ca kvm: Add checkpoint debug print
Add a debug print (when the Checkpoint debug flag is set) on serialize
and unserialize. Additionally, dump the KVM state before
serializing. The KVM state isn't dumped after unserializing since the
state is loaded lazily on the next KVM entry.
2013-05-02 12:02:19 +02:00
Andreas Sandberg
41156c8196 kvm: Make MMIO requests uncacheable
Device accesses are normally uncacheable. This change probably doesn't
make any difference since we normally disable caching when KVM is
active. However, there might be devices that check this, so we'd
better enable this flag to be safe.
2013-05-02 12:01:50 +02:00
Andreas Sandberg
12d7498ad5 sim: Add support for m5fail in pseudoInst() 2013-05-02 11:54:08 +02:00
Andreas Hansson
9f8b1aec49 config: Added memory type to t1000 regression
This patch adds the memory type parameter to the t1000 regression.
2013-04-28 17:14:39 -04:00
Michael Levenhagen
223f89a162 x86: corrects vsyscall address for gettimeofday
The vsyscall address for gettimeofday is 0xffffffffff600000ul. The offset
therefore should be 0x0 instead of 0x410. This can be cross checked with
the file sysdeps/unix/sysv/linux/x86_64/gettimeofday.c in source of glibc.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-04-23 15:21:32 -05:00
Michael Levenhagen
794d00257a x86: enable gettimeofday and getppid system calls
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-04-23 15:21:30 -05:00
Marco Elver
0c57194a09 config: Fix mem-type option not used in ruby_fs script
This fixes missing mem-type arguments to makeLinuxAlphaRubySystem and
makeLinuxX86System after a recent changeset allowing mem-type to be
configured via options missed fixing these calls.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-04-23 11:56:48 -05:00
Mitch Hayenga
b222ba2fd3 sim: Fix two bugs relating to software caching of PageTable entries.
The existing implementation can read uninitialized data or stale information
from the cached PageTable entries.

1) Add a valid bit for the cache entries.  Simply using zero for the virtual
address to signify invalid entries is not sufficient.  Speculative, wrong-path
accesses frequently access page zero.  The current implementation would return
a uninitialized TLB entry when address zero was accessed and the PageTable
cache entry was invalid.

2) When unmapping/mapping/remaping a page, invalidate the corresponding
PageTable cache entry if one already exists.
2013-04-23 09:47:52 -04:00
Andreas Hansson
3e35fa5dcc cpu: Fix TraceGen flag initalisation
This patch ensures the flags are always initialised.
2013-04-23 05:07:10 -04:00
Nilay Vaish
c2d799c6b0 x86: regressions: add switcher full test 2013-04-23 00:03:09 -05:00
Nilay Vaish
95eebf9e5e ruby: mesi coherence protocol: remove unused state M_MB 2013-04-23 00:03:07 -05:00
Nilay Vaish
3295e6de69 x86, stats: updates due to lret bugfix 2013-04-23 00:03:05 -05:00
Christian Menard
25a6b1866e x86: increment the stack pointer in lret inst
The 'lret' instruction reloads instruction pointer and code segment from the
stack and then pops them. But the popping part is missing from the current
implementation. This caused incorrect behavior in some code related to the
Fiasco OS. Microops are being added to rectify the behavior of the instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-04-23 00:03:04 -05:00
Nilay Vaish
aa86800e7a ruby: patch checkpoint restore with garnet
Due to recent changes to clocking system in Ruby and the way Ruby restores
state from a checkpoint, garnet was failing to run from a checkpointed state.
The problem is that Ruby resets the time to zero while warming up the caches.
If any component records a local copy of the time (read calls curCycle())
before the simulation has started, then that component will not operate until
that time is reached. In the context of this particular patch, the Garnet
Network class calls curCycle() at multiple places. Any non-operational
component can block in requests in the memory system, which the system
interprets as a deadlock. This patch makes changes so that Garnet can
successfully run from checkpointed state.

It adds a globally visible time at which the actual execution started. This
time is initialized in RubySystem::startup() function. This variable is only
meant for components with in Ruby. This replaces the private variable that
was maintained within Garnet since it is not possible to figure out the
correct time when the value of this variable can be set.

The patch also does away with all cases where curCycle() is called with in
some Ruby component before the system has actually started executing. This
is required due to the quirky manner in which ruby restores from a checkpoint.
2013-04-23 00:03:02 -05:00
Andreas Hansson
e23e3bea8b mem: Address mapping with fine-grained channel interleaving
This patch adds an address mapping scheme where the channel
interleaving takes place on a cache line granularity. It is similar to
the existing RaBaChCo that interleaves on a DRAM page, but should give
higher performance when there is less locality in the address
stream.
2013-04-22 13:20:34 -04:00
Andreas Hansson
e61799aa7c mem: More descriptive enum names for address mapping
This patch changes the slightly ambigious names used for the address
mapping scheme to be more descriptive, and actually spell out what
they do. With this patch we also open up for adding more flavours of
open- and close-type mappings, i.e. interleaving across channels with
the open map.
2013-04-22 13:20:33 -04:00
Andreas Hansson
99b3a12a75 cpu: Use request flags in trace playback
This patch changes the TraceGen such that it uses the optional request
flags from the protobuf trace if they are present.
2013-04-22 13:20:33 -04:00
Andreas Hansson
fe97f0e2b1 cpu: Make the generators usable outside the TrafficGen module
This patch enables the use of the generator behaviours outside the
TrafficGen module. This is useful e.g. to allow packet replay modes
for other devices in the system without having to replace them with a
TrafficGen in the configuration files.

This change also enables more specific behaviours to be composed as
specific modules, e.g. BaseBandModem can use a number of generators
and have application-specific parameters based around a specific set
of generators.
2013-04-22 13:20:33 -04:00
Andreas Hansson
3477d60d5c config: Add a mem-type config option to se/fs scripts
This patch enables selection of the memory controller class through a
mem-type command-line option. Behind the scenes, this option is
treated much like the cpu-type, and a similar framework is used to
resolve the valid options, and translate the short-hand description to
a valid class.

The regression scripts are updated with a hardcoded memory class for
the moment. The best solution going forward is probably to get the
memory out of the makeSystem functions, but Ruby complicates things as
it does not connect the memory controller to the membus.

--HG--
rename : configs/common/CpuConfig.py => configs/common/MemConfig.py
2013-04-22 13:20:33 -04:00
Andreas Hansson
a35d3ff167 mem: Add a WideIO DRAM configuration
This patch adds a WideIO 200 MHz configuration that can be used as a
baseline to compare with DDRx and LPDDRx. Note that it is a single
channel and that it should be replicated 4 times. It is based on
publically available information and attempts to capture an envisioned
8 Gbit single-die part (i.e. without TSVs).
2013-04-22 13:20:33 -04:00
Uri Wiener
a8fbfefb5e mem: Adding verbose debug output in the memory system
This patch provides useful printouts throughut the memory system. This
includes pretty-printed cache tags and function call messages
(call-stack like).
2013-04-22 13:20:33 -04:00
Andreas Hansson
9929e884b6 mem: Replace check with panic where inhibited should not happen
This patch changes the SimpleTimingPort and RubyPort to panic on
inhibited requests as this should never happen in either of the
cases. The SimpleTimingPort is only used for the I/O devices PIO port
and the DMA devices config port and should thus never see an inhibited
request. Similarly, the SimpleTimingPort is also used for the
MessagePort in x86, and there should also not be any cases where the
port sees an inhibited request.
2013-04-22 13:20:33 -04:00
Ali Saidi
d69f904a18 stats: Update stats for O3 switching fix. 2013-04-22 13:20:33 -04:00
Andreas Sandberg
33ab8f735d kvm: Add support for pseudo-ops on ARM
This changeset adds support for m5 pseudo-ops when running in
kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor
entry in KVM (it doesn't seem to be possible to trap accesses to
non-existing co-processors). We therefore use BZJ instructions to
cause a trap from virtualized mode into gem5. The BZJ instruction is
becomes a normal branch to the gem5 fallback code when running in
simulated mode, which means that this patch does not need to change
the ARM ISA-specific code.

Note: This requires a patched host kernel.
2013-04-22 13:20:32 -04:00
Andreas Sandberg
1c529a4196 sim: Add a helper function to execute pseudo instructions
All architectures execute m5 pseudo instructions by setting up
arguments according to the ABI and executing a magic instruction that
contains an operation number. Handling of such instructions is
currently spread across the different ISA implementations. This
changeset introduces the PseudoInst::pseudoInst function which handles
most of this in an architecture independent way. This is function is
mainly intended to be used from KVM, but can also be used from the
simulated CPUs.
2013-04-22 13:20:32 -04:00
Andreas Sandberg
32ecd72b6e kvm: Add support for state dumping on ARM 2013-04-22 13:20:32 -04:00
Andreas Sandberg
f156020158 kvm: Add basic support for ARM
Architecture specific limitations:
 * LPAE is currently not supported by gem5. We therefore panic if LPAE
   is enabled when returning to gem5.
 * The co-processor based interface to the architected timer is
   unsupported. We can't support this due to limitations in the KVM
   API on ARM.
 * M5 ops are currently not supported. This requires either a kernel
   hack or a memory mapped device that handles the guest<->m5
   interface.
2013-04-22 13:20:32 -04:00