kvm: Add support for pseudo-ops on ARM
This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
This commit is contained in:
Andreas Sandberg
parent
1c529a4196
commit
33ab8f735d
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@ -49,6 +49,7 @@
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#include "debug/Kvm.hh"
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#include "debug/KvmContext.hh"
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#include "debug/KvmInt.hh"
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#include "sim/pseudo_inst.hh"
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using namespace ArmISA;
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@ -310,6 +311,26 @@ ArmKvmCPU::updateThreadContext()
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updateTCStateMisc();
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}
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Tick
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ArmKvmCPU::onKvmExitHypercall()
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{
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ThreadContext *tc(getContext(0));
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const uint32_t reg_ip(tc->readIntRegFlat(INTREG_R12));
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const uint8_t func((reg_ip >> 8) & 0xFF);
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const uint8_t subfunc(reg_ip & 0xFF);
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DPRINTF(Kvm, "KVM Hypercall: 0x%x/0x%x\n", func, subfunc);
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const uint64_t ret(PseudoInst::pseudoInst(getContext(0), func, subfunc));
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// Just set the return value using the KVM API instead of messing
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// with the context. We could have used the context, but that
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// would have required us to request a full context sync.
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setOneReg(REG_CORE32(usr_regs.ARM_r0), ret & 0xFFFFFFFF);
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setOneReg(REG_CORE32(usr_regs.ARM_r1), (ret >> 32) & 0xFFFFFFFF);
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return 0;
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}
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const ArmKvmCPU::RegIndexVector &
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ArmKvmCPU::getRegList() const
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{
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@ -94,6 +94,8 @@ class ArmKvmCPU : public BaseKvmCPU
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void updateKvmState();
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void updateThreadContext();
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Tick onKvmExitHypercall();
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/**
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* Get a list of registers supported by getOneReg() and setOneReg().
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*/
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@ -40,122 +40,80 @@
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* Authors: Nathan Binkert
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* Ali Saidi
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* Chander Sudanthi
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* Andreas Sandberg
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*/
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.syntax unified
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#ifdef __thumb__
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.thumb
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#endif
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#define m5_op 0xEE
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#include "m5ops.h"
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#ifdef __thumb__
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#define INST(op, ra, rb, func) \
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.short (((op) << 8) | (func)); \
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.short (((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb))
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/* m5ops m5func */
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/* ra coproc 1 op=1 rb */
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#else
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#define INST(op, ra, rb, func) \
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.long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb))
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/* m5ops m5func ra coproc 1 op=1 rb */
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#endif
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#define LEAF(func) \
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.globl func; \
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func:
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#define RET \
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mov pc,lr
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#define END(func) \
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#define SIMPLE_OP(_f, _o) \
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LEAF(_f) \
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_o; \
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RET; \
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END(_f)
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#define ARM INST(m5_op, 0, 0, arm_func)
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#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
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#define QUIESCENS INST(m5_op, 0, 0, quiescens_func)
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#define QUIESCECYC INST(m5_op, 0, 0, quiescecycle_func)
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#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
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#define RPNS INST(m5_op, 0, 0, rpns_func)
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#define WAKE_CPU INST(m5_op, 0, 0, wakecpu_func)
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#define M5EXIT INST(m5_op, 0, 0, exit_func)
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#define INITPARAM INST(m5_op, 0, 0, initparam_func)
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#define LOADSYMBOL INST(m5_op, 0, 0, loadsymbol_func)
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#define RESET_STATS INST(m5_op, 0, 0, resetstats_func)
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#define DUMP_STATS INST(m5_op, 0, 0, dumpstats_func)
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#define DUMPRST_STATS INST(m5_op, 0, 0, dumprststats_func)
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#define CHECKPOINT INST(m5_op, 0, 0, ckpt_func)
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#define READFILE INST(m5_op, 0, 0, readfile_func)
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#define WRITEFILE INST(m5_op, 0, 0, writefile_func)
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#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
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#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
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#define ADDSYMBOL INST(m5_op, 0, 0, addsymbol_func)
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#define PANIC INST(m5_op, 0, 0, panic_func)
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#define WORK_BEGIN INST(m5_op, 0, 0, work_begin_func)
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#define WORK_END INST(m5_op, 0, 0, work_end_func)
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#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
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#define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
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#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func)
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#define AN_END INST(m5_op, an_end, 0, annotate_func)
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#define AN_Q INST(m5_op, an_q, 0, annotate_func)
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#define AN_RQ INST(m5_op, an_rq, 0, annotate_func)
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#define AN_DQ INST(m5_op, an_dq, 0, annotate_func)
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#define AN_WF INST(m5_op, an_wf, 0, annotate_func)
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#define AN_WE INST(m5_op, an_we, 0, annotate_func)
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#define AN_WS INST(m5_op, an_ws, 0, annotate_func)
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#define AN_SQ INST(m5_op, an_sq, 0, annotate_func)
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#define AN_AQ INST(m5_op, an_aq, 0, annotate_func)
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#define AN_PQ INST(m5_op, an_pq, 0, annotate_func)
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#define AN_L INST(m5_op, an_l, 0, annotate_func)
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#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func)
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#define AN_GETID INST(m5_op, an_getid, 0, annotate_func)
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.text
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SIMPLE_OP(arm, ARM)
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SIMPLE_OP(quiesce, QUIESCE)
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SIMPLE_OP(quiesceNs, QUIESCENS)
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SIMPLE_OP(quiesceCycle, QUIESCECYC)
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SIMPLE_OP(quiesceTime, QUIESCETIME)
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SIMPLE_OP(rpns, RPNS)
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SIMPLE_OP(wakeCPU, WAKE_CPU)
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SIMPLE_OP(m5_exit, M5EXIT)
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SIMPLE_OP(m5_initparam, INITPARAM)
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SIMPLE_OP(m5_loadsymbol, LOADSYMBOL)
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SIMPLE_OP(m5_reset_stats, RESET_STATS)
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SIMPLE_OP(m5_dump_stats, DUMP_STATS)
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SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS)
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SIMPLE_OP(m5_checkpoint, CHECKPOINT)
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SIMPLE_OP(m5_readfile, READFILE)
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SIMPLE_OP(m5_writefile, WRITEFILE)
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SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
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SIMPLE_OP(m5_switchcpu, SWITCHCPU)
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SIMPLE_OP(m5_addsymbol, ADDSYMBOL)
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SIMPLE_OP(m5_panic, PANIC)
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SIMPLE_OP(m5_work_begin, WORK_BEGIN)
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SIMPLE_OP(m5_work_end, WORK_END)
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.macro simple_op name, func, subfunc
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.globl \name
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\name:
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/* First, try to trap into m5 using the m5-kvm hypercall
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* hack. The bxj will become a branch to the fallback code
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* if it is executed in the normal m5 environment.
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*/
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push {lr}
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ldr lr, =1f
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ldr ip, =((((\func) & 0xFF) << 8) | ((\subfunc) & 0xFF))
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bxj lr
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pop {pc}
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SIMPLE_OP(m5a_bsm, AN_BSM)
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SIMPLE_OP(m5a_esm, AN_ESM)
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SIMPLE_OP(m5a_begin, AN_BEGIN)
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SIMPLE_OP(m5a_end, AN_END)
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SIMPLE_OP(m5a_q, AN_Q)
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SIMPLE_OP(m5a_rq, AN_RQ)
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SIMPLE_OP(m5a_dq, AN_DQ)
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SIMPLE_OP(m5a_wf, AN_WF)
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SIMPLE_OP(m5a_we, AN_WE)
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SIMPLE_OP(m5a_ws, AN_WS)
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SIMPLE_OP(m5a_sq, AN_SQ)
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SIMPLE_OP(m5a_aq, AN_AQ)
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SIMPLE_OP(m5a_pq, AN_PQ)
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SIMPLE_OP(m5a_l, AN_L)
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SIMPLE_OP(m5a_identify, AN_IDENTIFY)
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SIMPLE_OP(m5a_getid, AN_GETID)
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/* Old-style m5 pseudo instruction using CP1 accesses */
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1:
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#ifdef __thumb__
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.short 0xEE00 | \func
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.short 0x0110 | (\subfunc << 12)
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#else
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#define INST(op, ra, rb, func) \
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.long (0xEE000110 | (\func << 16) | (\subfunc << 12)
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#endif
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pop {pc}
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.endm
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#define SIMPLE_OP(name, func, subfunc) simple_op name, func, subfunc
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SIMPLE_OP(arm, arm_func, 0)
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SIMPLE_OP(quiesce, quiesce_func, 0)
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SIMPLE_OP(quiesceNs, quiescens_func, 0)
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SIMPLE_OP(quiesceCycle, quiescecycle_func, 0)
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SIMPLE_OP(quiesceTime, quiescetime_func, 0)
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SIMPLE_OP(rpns, rpns_func, 0)
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SIMPLE_OP(wakeCPU, wakecpu_func, 0)
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SIMPLE_OP(m5_exit, exit_func, 0)
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SIMPLE_OP(m5_initparam, initparam_func, 0)
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SIMPLE_OP(m5_loadsymbol, loadsymbol_func, 0)
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SIMPLE_OP(m5_reset_stats, resetstats_func, 0)
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SIMPLE_OP(m5_dump_stats, dumpstats_func, 0)
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SIMPLE_OP(m5_dumpreset_stats, dumprststats_func, 0)
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SIMPLE_OP(m5_checkpoint, ckpt_func, 0)
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SIMPLE_OP(m5_readfile, readfile_func, 0)
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SIMPLE_OP(m5_writefile, writefile_func, 0)
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SIMPLE_OP(m5_debugbreak, debugbreak_func, 0)
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SIMPLE_OP(m5_switchcpu, switchcpu_func, 0)
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SIMPLE_OP(m5_addsymbol, addsymbol_func, 0)
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SIMPLE_OP(m5_panic, panic_func, 0)
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SIMPLE_OP(m5_work_begin, work_begin_func, 0)
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SIMPLE_OP(m5_work_end, work_end_func, 0)
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SIMPLE_OP(m5a_bsm, annotate_func, an_bsm)
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SIMPLE_OP(m5a_esm, annotate_func, an_esm)
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SIMPLE_OP(m5a_begin, annotate_func, an_begin)
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SIMPLE_OP(m5a_end, annotate_func, an_end)
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SIMPLE_OP(m5a_q, annotate_func, an_q)
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SIMPLE_OP(m5a_rq, annotate_func, an_rq)
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SIMPLE_OP(m5a_dq, annotate_func, an_dq)
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SIMPLE_OP(m5a_wf, annotate_func, an_wf)
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SIMPLE_OP(m5a_we, annotate_func, an_we)
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SIMPLE_OP(m5a_ws, annotate_func, an_ws)
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SIMPLE_OP(m5a_sq, annotate_func, an_sq)
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SIMPLE_OP(m5a_aq, annotate_func, an_aq)
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SIMPLE_OP(m5a_pq, annotate_func, an_pq)
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SIMPLE_OP(m5a_l, annotate_func, an_l)
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SIMPLE_OP(m5a_identify, annotate_func, an_identify)
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SIMPLE_OP(m5a_getid, annotate_func, an_getid)
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