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Author SHA1 Message Date
Steve Reinhardt
9d6d31de72 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-newtests

--HG--
extra : convert_revision : ab7e77844985372cc69899066fb26bee864598d2
 2006-08-16 14:45:34 -04:00
Kevin Lim
f287c68042 Add in contributions. 
--HG--
extra : convert_revision : 2f71f772f8fba536aa2d8f2beb6039b3fda9bbfc
 2006-08-16 14:45:34 -04:00
Steve Reinhardt
7ecc7f5083 Update reference outputs 
--HG--
extra : convert_revision : df9cf835e0910df1e8e80152825fde9327d4aadb
 2006-08-16 14:45:12 -04:00
Steve Reinhardt
bd4ccd6e39 Finish test clean-up & reorg. 
configs/common/FSConfig.py:
    Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
    make it work again
src/python/m5/objects/BaseCPU.py:
    Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
    Increase default stack size so we don't get an
    'increasing stack' message on 'hello world'
tests/SConscript:
    Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
    don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
    fix
tests/run.py:
    move configs to separate dir

--HG--
rename : configs/test/fs.py => configs/example/fs.py
rename : configs/test/test.py => configs/example/se.py
rename : tests/simple-atomic.py => tests/configs/simple-atomic.py
rename : tests/simple-timing.py => tests/configs/simple-timing.py
rename : tests/linux-mpboot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
rename : tests/linux-mpboot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
rename : tests/linux-mpboot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
rename : tests/linux-boot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/linux-boot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
rename : tests/linux-boot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
rename : tests/linux-boot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
rename : tests/linux-boot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
rename : tests/linux-boot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
rename : tests/linux-mpboot/ref/alpha/timing/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/timing/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
rename : tests/linux-mpboot/ref/alpha/timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
rename : tests/linux-mpboot/ref/alpha/timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
rename : tests/test-progs/hello/bin/mips/linux/hello_mips => tests/test-progs/hello/bin/mips/linux/hello
rename : tests/test-progs/hello/bin/sparc/bin => tests/test-progs/hello/bin/sparc/linux/hello
extra : convert_revision : d68ee6d7eefa7ba57370f3fb3c3589f86a6ea6b4
 2006-08-16 14:42:44 -04:00
Steve Reinhardt
3298c0b222 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-newtests

--HG--
extra : convert_revision : 8b4b1529fc20d6fa94cb6e2bd5ff25c984e722f5
 2006-08-16 14:22:44 -04:00
Gabe Black
47f545881e Added the SPARC ISA as a contribution. 
--HG--
extra : convert_revision : 74b061a14436425b2ac475bb498d71105bfa8e01
 2006-08-16 13:46:22 -04:00
Lisa Hsu
2b273a9ba9 AUTHORS: 
author file contribution

AUTHORS:
    author file contribution

--HG--
extra : convert_revision : f4a08695fb4bf37df6144529c5791c75c11a0515
 2006-08-16 13:46:21 -04:00
Steve Reinhardt
2552e68eb6 More restructuring of regression tests. 
Moving work back to zizzer...

configs/common/FSConfig.py:
configs/test/fs.py:
    Move CPU connections out of makeLinuxAlphaSystem()
src/python/m5/objects/BaseCPU.py:
    Create default TLBs in full system.
    Move utility cache functions here.
src/python/m5/objects/O3CPU.py:
    Add _mem_ports
tests/run.py:
    Add binpath()
    Change maxtick default to 'forever'
tests/simple-atomic.py:
    Use connectmemPorts()
tests/simple-timing.py:
    Fix up.

--HG--
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.ini => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.out => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
rename : tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
rename : tests/quick/eio1/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
rename : tests/quick/eio1/test.py => tests/quick/20.eio-short/test.py
rename : configs/test/hello => tests/test-progs/hello/bin/alpha/linux/hello
rename : configs/test/hello_mips => tests/test-progs/hello/bin/mips/linux/hello_mips
rename : configs/test/sparc_tests/hello_sparc => tests/test-progs/hello/bin/sparc/bin
extra : convert_revision : 1f891392ecc11ffcc3b3182fa673c401c0efc8a5
 2006-08-16 09:52:05 -07:00
Ali Saidi
495ac606dd fix e-mail addr in readme 
--HG--
extra : convert_revision : 2cd6dd468f7c45f09707d311e43168f9b3470ab3
 2006-08-16 11:01:37 -04:00
Steve Reinhardt
bb9d2c3457 Halfway through setting up new test structure... committing so 
O can move to my laptop.

tests/SConscript:
    Start to simplify.

--HG--
rename : tests/test1/ref/alpha/detailed/config.ini => tests/quick/eio1/ref/alpha/eio/detailed/config.ini
rename : tests/test1/ref/alpha/detailed/config.out => tests/quick/eio1/ref/alpha/eio/detailed/config.out
rename : tests/test1/ref/alpha/detailed/m5stats.txt => tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt
rename : tests/test1/ref/alpha/detailed/stderr => tests/quick/eio1/ref/alpha/eio/detailed/stderr
rename : tests/test1/ref/alpha/detailed/stdout => tests/quick/eio1/ref/alpha/eio/detailed/stdout
rename : tests/test1/ref/alpha/atomic/config.ini => tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini
rename : tests/test1/ref/alpha/atomic/config.out => tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out
rename : tests/test1/ref/alpha/atomic/m5stats.txt => tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt
rename : tests/test1/ref/alpha/atomic/stderr => tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr
rename : tests/test1/ref/alpha/atomic/stdout => tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout
rename : tests/test1/ref/alpha/timing/config.ini => tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini
rename : tests/test1/ref/alpha/timing/config.out => tests/quick/eio1/ref/alpha/eio/simple-timing/config.out
rename : tests/test1/ref/alpha/timing/m5stats.txt => tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt
rename : tests/test1/ref/alpha/timing/stderr => tests/quick/eio1/ref/alpha/eio/simple-timing/stderr
rename : tests/test1/ref/alpha/timing/stdout => tests/quick/eio1/ref/alpha/eio/simple-timing/stdout
extra : convert_revision : 924d2ee29d2a2709135ff8e5c5822fe47a8a60f6
 2006-08-16 09:45:46 -04:00
Gabe Black
da6649fa71 Tweaks to Ali's changes 
--HG--
extra : convert_revision : ca2a81dd38012ae780f88cfd6be60f21fb43bb81
 2006-08-15 19:17:18 -04:00
Ali Saidi
de29f555c4 implement benchmark selection code 
--HG--
extra : convert_revision : 84632fdad7019e177e61c56ae30ea2f3fdbc0995
 2006-08-15 19:12:19 -04:00
Ali Saidi
4c3e01bd90 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/tmp/m5.newmem

--HG--
extra : convert_revision : d490a68eeabd0da7cd9791e14ca3678ed0fd31e6
 2006-08-15 17:41:37 -04:00
Ali Saidi
ed58f77c47 fixes for gcc 4.1 
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa

OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset

README:
    Fix the swig version in the readme
src/SConscript:
    remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
    fixes for gcc 4.1

--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
 2006-08-15 17:41:22 -04:00
Ron Dreslinski
890f0fc782 Merge zizzer:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 27bfbce7c674f0628ef53921329c08f31db6ef44
 2006-08-15 16:35:12 -04:00
Ron Dreslinski
47b1c80502 Make test1 capable of running with caches (-C, --caches) for testing. 
--HG--
extra : convert_revision : 0b018f9e33b83c346ca0fb1b4e4066fb80c96b8c
 2006-08-15 16:24:01 -04:00
Ron Dreslinski
d5ac1cb51f Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches. 
-Basically removed the ASID from places it is no longer needed due to PageTable

src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
    Remove asid where it wasn't neccesary anymore due to Page Table

--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
 2006-08-15 16:21:46 -04:00
Steve Reinhardt
65d00083ef README: 
Fix SWIG version number.

README:
    Fix SWIG version number.

--HG--
extra : convert_revision : 618d6e63d44bc7664dace545d4e35119f52b8407
 2006-08-15 15:43:00 -04:00
Ron Dreslinski
d0d0d7b636 Merge zizzer:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 8a8d7fe59610806015c8242a2f5eacf9afce7164
 2006-08-15 14:28:22 -04:00
Ron Dreslinski
dc375e42bc Some changes to support blocking in the caches 
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache_impl.hh:
    Outstanding blocking updates for cache

--HG--
extra : convert_revision : 3a7b4aa4921de8239f604f1852f262a2305862c0
 2006-08-15 14:24:49 -04:00
Steve Reinhardt
0748851071 Update release files. 
README:
    Add brief build instructions for the impatient.
    A few minor fixes.
RELEASE_NOTES:
    Change date; add beta disclaimer.

--HG--
extra : convert_revision : d31af687c657feb36a2694ef9f0abd67390c7023
 2006-08-15 08:49:15 -07:00
Gabe Black
74e80fc6c7 Some touchup to the reorganized includes and "using" directives. 
--HG--
extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
 2006-08-15 05:49:52 -04:00
Gabe Black
cd6eb53965 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  ewok.(none):/home/gblack/m5/newmem

src/cpu/static_inst.hh:
    SCCS merged

--HG--
extra : convert_revision : a4f6377dbd691ab58fe5f7958b983b092575f250
 2006-08-15 05:08:30 -04:00
Gabe Black
74546aac01 Cleaned up include files and got rid of many using directives in header files. 
--HG--
extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
 2006-08-15 05:07:15 -04:00
Gabe Black
c9900f159e Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alpha/pagetable.hh and fixing up some includes 
--HG--
extra : convert_revision : 02a47fa62b17245763314890beb68339c789d18f
 2006-08-15 04:46:51 -04:00
Steve Reinhardt
336beeaf43 More cleanup for release. 
--HG--
extra : convert_revision : 94b45da5d1a658c4d0f87c73ce72facc9da8d981
 2006-08-15 02:08:25 -04:00
Steve Reinhardt
5bd07f98ed Fix up doxygen. 
--HG--
rename : docs/footer.html => src/doxygen/footer.html
rename : docs/stl.hh => src/doxygen/stl.hh
extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
 2006-08-14 19:25:07 -04:00
Steve Reinhardt
a04552ce86 Changes for release. 
README:
    s/m5.eecs.umich.edu/www.m5sim.org/
    whack mentions of "CD distribution"
RELEASE_NOTES:
    Set date of 2.0 beta release
    Fix typo

--HG--
extra : convert_revision : 5baa113a98f89dbf56f60adb4513ca22b63673b1
 2006-08-14 18:15:53 -04:00
Gabe Black
741bc40cc3 Changed the size parameter from int to int64_t 
--HG--
extra : convert_revision : a19404bdc3a6434fe28f8aa278dc6addf764be22
 2006-08-14 03:18:38 -04:00
Gabe Black
fc8b4f5253 Started to add support for O3 for sparc. 
--HG--
extra : convert_revision : 3f94bda14024a09b9fbd7a5d13284d4987349ddf
 2006-08-11 20:29:15 -04:00
Gabe Black
95dc8e4d57 Changed the compiler guards to say SPARC 
--HG--
extra : convert_revision : e79964148c7fb7075627f46add6687f6cd0ee241
 2006-08-11 20:28:35 -04:00
Gabe Black
fb35d474a5 Added code to support setting up all of the auxillieary vectors configured by the sparc linux elf loader. 
src/arch/sparc/process.cc:
    All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow.

--HG--
extra : convert_revision : 4a90cacf70b1032cad3f18b0f833a6df8237e0de
 2006-08-11 20:27:22 -04:00
Gabe Black
1f44717732 #include of iostream needed. 
--HG--
extra : convert_revision : d31bb943ab25103cf715159054df318a5b88abc9
 2006-08-11 20:23:31 -04:00
Gabe Black
e6842652ba Adjusted the decoder a little. 
--HG--
extra : convert_revision : 5bdbe00342837ae4caacb3ad86c7becca36ba6ce
 2006-08-11 20:22:36 -04:00
Gabe Black
ec26f0bb3d Started adding a system to output data after every instruction. 
src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
    Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
    Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
    Options to turn on output after every instruction. They are commented out.

--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
 2006-08-11 20:21:35 -04:00
Gabe Black
800e6ecc07 Pushed most of constants.hh back into isa_traits.hh and regfile.hh and created a seperate file for the syscallreturn class. 
--HG--
extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
 2006-08-11 19:43:10 -04:00
Korey Sewell
f612f09669 make test3.py usable again ... I guess I should fix up test4 and test5 too??? 
Also, What happened to the "lets make real names for these tests" thing we
were talking about? Is test1 - test(n) OK now?

--HG--
extra : convert_revision : 60716e41ecc79a78241be383ab3cae4b9e382335
 2006-08-11 18:42:43 -04:00
Kevin Lim
de321175f2 Add in a bunch more stuff. 
configs/boot/micro_memlat.rcS:
    Update these scripts so they work (not sure why they broke)
configs/boot/micro_tlblat.rcS:
    Update this script to use a different test.

--HG--
extra : convert_revision : 6e8692540a9fac6ae8f2d9975c70d4135354b849
 2006-08-11 17:48:41 -04:00
Kevin Lim
716ceb6c10 Code update for CPU models. 
arch/alpha/isa_traits.hh:
    Add in clear functions.
cpu/base.cc:
cpu/base.hh:
    Add in CPU progress event.
cpu/base_dyn_inst.hh:
    Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
    Allow for progress intervals.
cpu/o3/tournament_pred.cc:
    Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
    Fixes.
cpu/ozone/cpu_builder.cc:
    Allow progress interval.
cpu/ozone/front_end_impl.hh:
    Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
    Remove this.
python/m5/objects/BaseCPU.py:
    Add progress interval.
python/m5/objects/Root.py:
    Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
    Add in stats reset.

--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
 2006-08-11 17:42:59 -04:00
Korey Sewell
9058175af9 really confused about this license but OK... 
--HG--
extra : convert_revision : 85e40593e344b9eff325061630db27d178937258
 2006-08-10 20:51:43 -04:00
Kevin Lim
5ec58c4bdc Fix up some ISA related stuff. 
arch/alpha/isa/decoder.isa:
    Marked a few more instructions as unverifiable.
arch/alpha/isa/mem.isa:
    Warn instead of panic, otherwise this can cause the simulation to fail even if the instruction is never committed.

--HG--
extra : convert_revision : 12befc6fedd1a6883d0517e649ad01b91fb561ae
 2006-08-02 12:07:44 -04:00
Kevin Lim
5be592f870 Make checker handle not executing the same instruction as the main CPU a little better. 
Also add the option for the checker to update itself with the main CPU's state if it executes an instruction differently (so it will handle DMA timing errors properly).

--HG--
extra : convert_revision : 760d11ec1a249bc75e2807d320866b5d08c2b6f2
 2006-08-02 12:06:59 -04:00
Kevin Lim
cbfbb7bc56 Updates to bring CPU portion of m5 up-to-date with newmem. 
--HG--
extra : convert_revision : 00e6eefb24e6ffd9c7c5d8165db26fbf6199fdc4
 2006-08-02 12:05:34 -04:00
Kevin Lim
8d220c5c10 Updates for registers and stuff. 
arch/alpha/ev5.cc:
    Update for copying IPRs.
arch/alpha/isa_traits.hh:
    Allow for misc register file to serialize.  Also add some register copying code.
cpu/cpu_exec_context.cc:
    Use ISA's function to copy registers.

--HG--
extra : convert_revision : 09fa3b2b1b229cbf3a34f69354953da2607c2a8f
 2006-08-02 12:04:18 -04:00
Kevin Lim
db6c908e0f Minor configuration updates. 
--HG--
extra : convert_revision : d638d440edd91caa31977eb6d2325c899962936f
 2006-08-02 11:56:06 -04:00
Kevin Lim
08c0919b43 Clean up some more config stuff. 
configs/common/FSConfig.py:
    Clean up some code to make functions look less like classes.  Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
    Update for changed code.
src/python/m5/__init__.py:
    Put makeList into m5.

--HG--
extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
 2006-07-27 17:49:00 -04:00
Kevin Lim
53e17d0368 Update ref stats. 
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/stderr:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/stdout:
    Updated output.

--HG--
extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
 2006-07-27 17:47:43 -04:00
Kevin Lim
94dd369fcd Output the command line. 
src/python/m5/main.py:
    Output the command line being used.

--HG--
extra : convert_revision : 51dadb0ef79ca1e8bbb5a3bd64110071c30ade0d
 2006-07-27 17:37:28 -04:00
Kevin Lim
52c3991182 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 70221af596bddbfcc40646d03f175ef5e4b75909
 2006-07-27 16:43:29 -04:00
Kevin Lim
64b7213046 Need config read/write latency. 
--HG--
extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
 2006-07-27 16:43:02 -04:00