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Author SHA1 Message Date
Jack Whitham
fce4412d76 ARM: Fix the "open" flag constants. 2009-07-14 21:03:33 -07:00
Polina Dudnik
289cd00326 Changed the state machine to generate code such that multiple processors can make atomic requests at once 2009-07-13 18:39:32 -05:00
Polina Dudnik
5f551d9ca2 1. Got rid of unused functions in DirectoryMemory 
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue

Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once
 2009-07-13 17:22:29 -05:00
Derek Hower
100da6b326 merge 2009-07-13 14:49:51 -05:00
Derek Hower
d51445490d regression: updated memtest-ruby stats 
This also includes a change to the default Ruby random seed, which was
previously set using the wall clock.  It is now set to 1234 so that
the stat files don't change for the regression tester.
 2009-07-13 14:45:15 -05:00
Polina Dudnik
9a675a0391 Changes to add tracing and replaying command-line options 
Trace is automatically ended upon a manual checkpoint
 2009-07-13 12:50:10 -05:00
Polina Dudnik
b28058917c Locked requests should actually be converted to ST rather than ATOMIC, because ATOMIC is for RMW. 2009-07-13 12:11:17 -05:00
Polina Dudnik
7a6bf67e47 Added atomics implementation which would work for MI_example 2009-07-13 12:06:23 -05:00
Polina Dudnik
c66af9f474 Minor fixes for compiling 2009-07-13 11:59:13 -05:00
Polina Dudnik
7606c71ea5 Replaced RMW with Locked. RMW will be used for the coherence-aided atomics other than LLSC 2009-07-13 11:37:56 -05:00
Polina Dudnik
faf823f947 Moved the lock check and clearing the lock into makeRequest 2009-07-13 11:34:38 -05:00
Polina Dudnik
86ce60e5cd Forgot to replace one of the RubyRequest_RMW 2009-07-13 11:25:23 -05:00
Polina Dudnik
226981b2a6 Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure 2009-07-13 11:13:29 -05:00
Gabe Black
60577eb4ca ISAs: Get rid of the IControl operand type. 
A separate operand type is not necessary to use two bitfields to generate the
index.
 2009-07-10 01:21:04 -07:00
Gabe Black
64fe7af51a SPARC: Set up a lookup table for integer register flattening. 
Using a look up table changed the run time of the SPARC_FS solaris boot
regression from:

real    14m45.951s
user    13m57.528s
sys     0m3.452s

to:

real    12m19.777s
user    12m2.685s
sys     0m2.420s
 2009-07-10 01:01:47 -07:00
Gabe Black
9993ca8280 X86: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:29:02 -07:00
Gabe Black
60d47aa5f9 SPARC: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:50 -07:00
Gabe Black
de7f462219 MIPS: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:39 -07:00
Gabe Black
e14c408b62 ARM: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:27 -07:00
Gabe Black
5643a222e3 Alpha: Missed a file in an earlier changeset. 2009-07-09 00:20:41 -07:00
Gabe Black
c9a27d85b9 Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
Gabe Black
3d39b62132 Alpha: Pull the MiscRegFile fully into the ISA object. 2009-07-08 23:02:22 -07:00
Gabe Black
b398b8ff1b Registers: Add a registers.hh file as an ISA switched header. 
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
 2009-07-08 23:02:21 -07:00
Gabe Black
997f36c711 Registers: Collapse ARM and MIPS regfile directories. 
--HG--
rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh
rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc
rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc
rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
 2009-07-08 23:02:21 -07:00
Gabe Black
aa031e1c11 Alpha: Move reg_redir into its own files, and move some constants into regfile.hh. 2009-07-08 23:02:21 -07:00
Gabe Black
5c37d10624 Registers: Eliminate the ISA defined RegFile class. 2009-07-08 23:02:21 -07:00
Gabe Black
9bf22992ee Alpha: Get rid of function prototypes with no implementations. 2009-07-08 23:02:21 -07:00
Gabe Black
43345bff6c Registers: Move the PCs out of the ISAs and into the CPUs. 2009-07-08 23:02:21 -07:00
Gabe Black
1b29f1621d ARM, Simple CPU: Fix an index and add assert checks. 2009-07-08 23:02:21 -07:00
Gabe Black
0338c83c9d MIPS: Get rid of an orphaned MIPS .cc file. 2009-07-08 23:02:21 -07:00
Gabe Black
6ebce9d65a Alpha: Phase out Alpha's intregfile.hh and intregfile.cc. 2009-07-08 23:02:21 -07:00
Gabe Black
faa6ebebe1 SPARC: Phase out SPARC's intregfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
ecde884404 X86: Phase out x86's intregfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
301df68c73 MIPS: Phase out MIPS's int_regfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
27b6148f47 ARM: Flush out the ARM's int_regfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
a480ba00b9 Registers: Eliminate the ISA defined integer register file. 2009-07-08 23:02:20 -07:00
Gabe Black
0cb180ea0d Registers: Eliminate the ISA defined floating point register file. 2009-07-08 23:02:20 -07:00
Gabe Black
25884a8773 Registers: Get rid of the float register width parameter. 2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f Registers: Add an ISA object which replaces the MiscRegFile. 
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
 2009-07-08 23:02:20 -07:00
Gabe Black
3e2cad8370 ARM: Use custom read/write code to alias R15 with the PC. 2009-07-08 23:02:20 -07:00
Gabe Black
b8b7c7314a ISA parser: Allow alternative read/write code for operands. 2009-07-08 23:02:19 -07:00
Gabe Black
95392d3fb8 ARM: Move the remaining microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black
1d4f338b39 ARM: Move the memory microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black
70a75ceb84 ARM: Move the integer microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black
4eb18cc07a ARM: Improve memory instruction disassembly. 2009-07-08 23:02:19 -07:00
Gabe Black
2fb8d481ab ARM: Tune up predicated instruction decoding. 2009-07-08 23:02:19 -07:00
Gabe Black
ddcf084f16 ARM: Get rid of the MemAcc and EAComp static insts. 2009-07-08 23:02:19 -07:00
Gabe Black
cae870eded ARM: Get rid of end_addr in the ArmMacroStore constructor. 2009-07-08 23:02:19 -07:00
Gabe Black
311f77f33d ARM: Add an AddrMode2 format for memory instructions that use address mode 2. 2009-07-08 23:02:19 -07:00
Gabe Black
826a3582ea ARM: Don't always update CPSR. 2009-07-08 23:02:19 -07:00