Ali Saidi
a17dbdf883
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 17:19:50 +00:00
Ali Saidi
44e599a1a4
ARM: Fix up stats for previous changes to condition codes
2011-05-13 17:29:27 -05:00
Nathan Binkert
8c1563096c
tests: update stats for name changes
2011-04-19 18:45:23 -07:00
Ali Saidi
b20e92e1ca
ARM: Update stats for previous changes.
2011-04-04 11:42:31 -05:00
Ali Saidi
63eb337b3b
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-17 19:20:22 -05:00
Gabe Black
0851580aad
Stats: Re update stats.
2011-02-07 19:23:13 -08:00
Ali Saidi
06c5283930
ARM: Update SE stats for TLB stats additions
2010-11-08 13:59:35 -06:00
Steve Reinhardt
13a15c55a4
stats: update stats for previous cset
...
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00
Steve Reinhardt
9e45ada171
stats: update stats for preceding coherence changes
...
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
Ali Saidi
e6d3fe8a0c
ARM: Update regression tests for ldr/str microcode changes.
2010-08-25 19:10:42 -05:00
Ali Saidi
1b73376b0b
ARM: Add regression tests
2010-07-27 01:03:44 -04:00
