sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
5393 commits 2 branches 0 tags 204 MiB
Commit graph

5393 commits

This branch
This branch
All branches
Author SHA1 Message Date
Gabe Black
93dd1978a7 X86: Put an RTC into the CMOS part of the southbridge. 
--HG--
extra : convert_revision : a614373236fe75db6e6181fc152a02b541a131f3
 2008-03-25 02:15:23 -04:00
Gabe Black
e5bdae15f3 Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it. 
--HG--
extra : convert_revision : 1e7f5185654ed0845678c2169c702d3b977159ed
 2008-03-25 02:15:06 -04:00
Gabe Black
af9a57566a X86: Turn #defines into consts. 
--HG--
extra : convert_revision : c0416de5d88ca39f54494418768e68a93aa4f2aa
 2008-03-25 02:09:18 -04:00
Gabe Black
48409ca512 X86: Start implementing the south bridge stuff. 
--HG--
extra : convert_revision : 92918c05eb3363155d78889bdab17baa8eae9dca
 2008-03-25 02:08:54 -04:00
Gabe Black
b0c52885ce X86: Change the Opteron platform to be the PC platform. 
--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
 2008-03-25 02:06:53 -04:00
Steve Reinhardt
623dd7ed3a Delete the Request for a no-response Packet 
when the Packet is deleted, since the requester
can't possibly do it.

--HG--
extra : convert_revision : 8571b144ecb3c70efc06d09faa8b3161fb58352d
 2008-03-24 01:08:02 -04:00
Steve Reinhardt
93ab43288a Don't FastAlloc MSHRs since we don't allocate them on the fly. 
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
 2008-03-24 01:08:02 -04:00
Steve Reinhardt
627592c2f2 Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options. 
--HG--
extra : convert_revision : 56a7f646f2ac87019c78ba7fa62c5f4bdc00ba44
 2008-03-24 01:08:02 -04:00
Steve Reinhardt
407710d387 Fix cache problem with writes to tempBlock 
getting wrong writeback address.

--HG--
extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b
 2008-03-22 22:17:15 -04:00
Gabe Black
3fe1af7952 MIPS: Check endianness of binaries in SE mode. 
--HG--
extra : convert_revision : e6c4bda6078eb68a26f8834411f744078c6bf5a9
 2008-03-20 02:10:21 -04:00
Steve Reinhardt
3de8a78a04 Update long regression stats for semi-recent cache changes. 
--HG--
extra : convert_revision : 7fef1e4f684ced37479ed363ebbb3a7485bc0d52
 2008-03-17 23:07:22 -04:00
Steve Reinhardt
b051ae6acc Fix a few Packet memory leaks. 
--HG--
extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a
 2008-03-17 03:08:28 -04:00
Steve Reinhardt
131c65f429 Restructure bus timing calcs to cope with pkt being deleted by target. 
--HG--
extra : convert_revision : db8497e73a44f2a06aab121e797e88b4c0c31330
 2008-03-17 03:07:38 -04:00
Steve Reinhardt
19c367fa8f Fix subtle cache bug where read could return stale data 
if a prior write miss arrived while an even earlier
read miss was still outstanding.

--HG--
extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
 2008-03-15 05:03:55 -07:00
Ali Saidi
969688154d Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist 
--HG--
extra : convert_revision : c156c49668815755c4c788f807e8eba32151aa24
 2008-03-15 22:20:09 -04:00
Gabe Black
50946b1673 Merge 
--HG--
extra : convert_revision : ec5f41b2007ade15f6f4c4a1533e50f9cba2798e
 2008-03-06 21:09:15 -05:00
Gabe Black
a245b0eedf X86: Refine the local APIC. 
--HG--
extra : convert_revision : 2789c54ed555fed2f2a333fcc7dc6454f294ebf2
 2008-03-06 20:37:28 -05:00
Vilas Sridharan
21fd15ad9a O3CPU: Don't call dumpInsts if DEBUG is not defined 
--HG--
extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
 2008-03-06 00:27:09 -05:00
Gabe Black
66aaabf4ae X86: Don't map the local APIC into the physical address space in SE mode. 
--HG--
extra : convert_revision : b7103974b12130bbf43583c4cb5294b808add208
 2008-03-01 00:05:12 -05:00
Ali Saidi
65332ef3a9 Added tag m5_2.0_beta4 for changeset cad8c2b5d2ec 
--HG--
extra : convert_revision : 3012e3c0393b8fd2f83e3532172269a27c0bbb04
 2008-02-29 18:08:49 -05:00
Ali Saidi
ead7dd4bb1 Added tag m5_2.0_beta5 for changeset fb826c79a385 
--HG--
extra : convert_revision : 13e2a028aaf899e2f314e6053266168b274e20fd
 2008-02-29 17:59:45 -05:00
Lisa Hsu
02a56d8d01 Error out if -s is used without --caches (instead of saying you must specify a 
CPU).

--HG--
extra : convert_revision : a3b2bfbe7e037146ac08dd08834bf255da692506
 2008-02-29 01:49:36 -05:00
Ali Saidi
0273533adb Configs: Make sure options don't conflict 
--HG--
extra : convert_revision : dc9b91cf1d8e33c5e68d7faeb45dbe3e7038d14c
 2008-02-29 01:23:18 -05:00
Ali Saidi
3cb7df428c Configs: Fix some bugs we introduced in the simpoints code 
--HG--
extra : convert_revision : ef22c11cb3242903a484fc05dc0f96d3e5f9af72
 2008-02-28 20:39:01 -05:00
Steve Reinhardt
19dfde2317 Automated merge with ssh://daystrom.m5sim.org//repo/m5 
--HG--
extra : convert_revision : f4bcd342e7abb86ca83840b723e6ab0b861ecf5b
 2008-02-27 18:18:56 -05:00
Steve Reinhardt
2f41006e44 Update outputs for quick tests to reflect fixed cache stats. 
Will update long tests later.

--HG--
extra : convert_revision : 79f66b5761a574f0c8049c1c771c353b42942993
 2008-02-27 18:17:37 -05:00
Korey Sewell
8fb74c238c Add comments in code to describe bug conditions. 
This should help if somebody gets to the bug
fix before me (or someone else)...

--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
 2008-02-27 17:50:29 -05:00
Korey Sewell
b45cf21a8e Fix Load/Store Queue squashing after a SMT thread is removed but ensuring 
you are squashing from the current instruction # causing the thread exit.

--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
 2008-02-27 16:53:08 -05:00
Korey Sewell
34715cc691 Fix offset in removeThread() function so that float registers start freeing up 
from the right point (#32 usually) instead of restarting at 0 and double-freeing.

Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.

--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
 2008-02-27 16:48:33 -05:00
Steve Reinhardt
e6d6adc731 Revamp cache timing access mshr check to make stats sane again. 
--HG--
extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
 2008-02-26 22:03:28 -08:00
Rick Strong
fcfc8b8c4f Configs: Make using Simpoints easier with some config files that support them easily 
--HG--
extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
 2008-02-27 00:35:09 -05:00
Gabe Black
43ecce5fda X86: Put in initial implementation of the local APIC. 
--HG--
extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8
 2008-02-26 23:39:53 -05:00
Gabe Black
98d2ca403e X86: Implement the INVLPG instruction and the TIA microop. 
--HG--
extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
 2008-02-26 23:39:22 -05:00
Gabe Black
8b4796a367 TLB: Make a TLB base class and put a virtual demapPage function in it. 
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
 2008-02-26 23:38:51 -05:00
Gabe Black
7bde0285e5 X86: Get PCI config space to work, and adjust address space prefix numbering scheme. 
--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
 2008-02-26 23:38:01 -05:00
Steve Reinhardt
bdf3323915 Cache: better comments particularly regarding writeback situation. 
--HG--
extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
 2008-02-26 20:17:26 -08:00
Ali Saidi
8c0baf2ce4 Update make release, README, and RELEASE_NOTES for b5 
--HG--
extra : convert_revision : a4958e934f599bff24b251507da7c266c89430fc
 2008-02-26 17:28:31 -05:00
Gabe Black
8833b4cd44 Bus: Update the stats for the recent bus fix. 
--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
 2008-02-26 02:20:40 -05:00
Gabe Black
ec1a4cbbc7 Bus: Fix the bus timing to be more realistic. 
--HG--
extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
 2008-02-26 02:20:08 -05:00
Vilas Sridharan
2e079ce038 add instruction count fast forwaing and max instruction options 
--HG--
extra : convert_revision : 8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
 2008-02-22 17:48:10 -05:00
Stephen Hines
ceee3ba96e Added ARM_SE as a build option. 
--HG--
extra : convert_revision : 905e3acfa58bd14f8101e29dadc0de71d23a79cc
 2008-02-19 16:42:32 -05:00
Steve Reinhardt
3204f96809 Update stats for new writeback behavior. 
--HG--
extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
 2008-02-16 14:58:37 -05:00
Steve Reinhardt
4597a71cef Make L2+ caches allocate new block for writeback misses 
instead of forwarding down the line.

--HG--
extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
 2008-02-16 14:58:03 -05:00
Steve Reinhardt
69ce7f953b Update stats for some unknown minor x86 changes 
(assuming someone just forgot to do this... tsk tsk).

--HG--
extra : convert_revision : 303d7bbf5e2c892d5f4498a9de2e2b82496ccd0e
 2008-02-16 13:53:12 -05:00
Ali Saidi
9faec83ac5 CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults. 
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
 2008-02-14 16:14:35 -05:00
Ali Saidi
fc38e9c630 Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency. 
--HG--
extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
 2008-02-14 16:13:50 -05:00
Ali Saidi
a33a3f7c55 Update copyright dates 
--HG--
extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1
 2008-02-11 12:35:28 -05:00
Steve Reinhardt
71835d42df Automated merge with file:/home/stever/hg/m5-orig 
--HG--
extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d
 2008-02-11 08:31:26 -08:00
Steve Reinhardt
2f7421b12b EXTRAS now points to src instead of needing 'src' subdir. 
--HG--
extra : convert_revision : 8e7e4516ace8c7852eeea3c479bfd567839a8061
 2008-02-11 08:04:01 -08:00
Steve Reinhardt
476a2ee950 Wait to set BUILD_DIR until *after* env is copied. 
--HG--
extra : convert_revision : 03153e7aaa1fb2a435900eab08a98ec1a6ce62db
 2008-02-11 07:47:44 -08:00