Distributed gem5 is the result of the convergence effort between
multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure
for packet forwarding, synchronisation and checkpointing but combines
those with the elaborated network switch model from pd-gem5.
A few warnings (and thus errors) pop up after being added to -Wall:
1. -Wmisleading-indentation
In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.
2. -Wshift-negative-value
gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.
That is all. Porting done.
Queued prefetcher entries now count with a priority field. The idea is to
add packets ordered by priority and then by age.
For the existing algorithms in which priority doesn't make sense, it is set
to 0 for all deferred packets in the queue.
Some common functionality added to the base prefetcher, mainly dealing with
extracting the block address, page address, block index inside the page and
some other information that can be inferred from the block address. This is
used for some prefetching algorithms, and having the methods in the base,
as well as the block size and other information is the sensible way.
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:
"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209
This is a re-spin of fb9d142 after the revert (bd1c6789).
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'. This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
This changeset updates the dot output to bail out if it is unable to
resolve the voltage or clock domains (which will cause it to raise an
AttributeError). Additionally, the DVFS dot output is disabled by
default for speed purposes.
Minor fixup for 0aeca8f.
The following patches had unexpected interactions with the current
upstream code and have been reverted for now:
e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:
"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'. This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
This patch adds some basic support for power models in gem5.
The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.
The model allows it to be extended to use other kinds of models.
Finally, the thermal model is updated to use the power usage as input.
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.
Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.
Add dump call back function to allow stats update of distribution and residency
stats.
This patch enables Linux to read the temperature using hwmon infrastructure.
In order to use this in your gem5 you need to compile the kernel using the
following configs:
CONFIG_HWMON=y
CONFIG_SENSORS_VEXPRESS=y
And a proper dts file (containing an entry such as):
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
temp@0 {
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
};
This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
This patch adds a secondary dot output file which shows the DVFS domains. This
has been done separately for now to avoid cluttering the already existing
diagram. Due to the way that the clock domains are assigned to components in
gem5, this output must be generated after the C++ objects have been
instantiated. This further motivates the need to generate this file separately
to the current dot output, and not to replace it entirely.
This patch adds some additional information when draining the system which
allows the user to debug which SimObject(s) in the system is failing to drain.
Only enabled for the builds with tracing enabled and is subject to the Drain
debug flag being set at runtime.
This patch addresses an issue with the unserialization of clock
domains. Previously, the previous performance level was not restored
due to a bug in the code, which detected the post-unserialize update
as superfluous. This patch splits the setting of the clock domain into
two parts. The original interface of perfLevel is retained, but the
actual update takes place in signalPerfLevelUpdate, which is private
to the class. The perfLevel method checks that if the new performance
level is different to the previous performance level, and will only
call signalPerfLevelUpdate if there is a change. Therefore, the
performance level is only updated, and voltage domains notified, if
there is an actual change. The split functionality allows
signalPerfLevelUpdate to be called by startup() to explicitly force an
update post unserialization.
This patch adds the ability for the simulator to query the number of
instructions a CPU has executed so far per hw-thread. This can be used
to enable more flexible periodic events such as taking checkpoints
starting 1s into simulation and X instructions thereafter.
The openFlagTable and mmapFlagTables for emulated Linux
platforms are basically identical, but are specified
repetitively for every platform. Use a common file
that gets included for each platform so that we only
have one copy, making them more consistent and simplifying
changes (like adding #ifdefs).
In the process, made some minor fixes that slipped through
due to previous inconsistencies, and added more #ifdefs
to try to fix building on alternative hosts.
The style refactor change (style: Refactor the style checker as a
Python package) moved region.py from src/python/m5/util/ to
util/style/. The SConscript update accidentally got lost in that
commit. This commit removes region.py from src/python/SConscript.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source : f69b75bf636dd4a4232af3e10c29f7eaa4d59dc8
The m5ops assembly library contains a lot of repetitive code. This
changeset adds two macros, FOREACH_M5OP and FOREACH_M5_ANNOTATION, to
m5ops.h that simplify architecture-specific implementations. The ARM
and ARMv8 m5op implementations have been updated to use the new
macros.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
The old style guide used to mandate 78 characters as the maximum line
length to accommodate traditional diffs on 80-column terminals. This
is an uncommon use case and it has therefore been decided (see email
thread on gem5-dev [1]) that a maximum length of 79-characters makes
more sense.
[1] http://comments.gmane.org/gmane.comp.emulators.m5.devel/29789
Signed-off-by: Andreas Sandberg <aandreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <brandon.potter@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
extra : rebase_source : 63efcc4da2585ef8c323d6f322736f64d71742f8
The current style checker script, hgstyle.py, assumes that it is being
run from Mercurial. This means that it depends on the Mercurial Python
libraries, which aren't necessarily present if using git. This
changeset adds a new style checker script, style.py, that has
been designed to be run from the command line.
The script has support for detecting which revision control system is
used and is able to query both git and Mercurial for changes. This
enables the script to operate on modified regions and/or all of the
modified files in the repository.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source : 2b420aff79d190f32557bc8822518cbc5d93e999
Add a check in the main SConscript that installs the git pre-commit
hook in util/ if git is used.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
[andreas.sandberg@arm.com: Cleanups suggested by Steve]
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source : 4b805cdd74bc5442a65abf8a62e3e341f352c04e
Add a git pre-commit hook that verifies that files that are about to
be committed. Since git stages changes into an index and the index
contains the changes that will be committed, the style checker only
looks at the state of files in the index.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source : 22a028bf13524cba188bd7896a0304f4c14ffeeb
Add an AbstractRepo class and implementations for git and Mercurial
that provide a common interface to query repository status for style
checkers. The class defines the interfaces to list modified files that
are about to be committed and methods to identify changed regions.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
extra : rebase_source : da1f482a1ecac2b0be437dc400b4a66bd3b301cc
Style validators provide a subset of the style verifier functionality
and are only exposed through the "hg m5format" command. This
functionality seems to be both redundant and unused.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : rebase_source : f4847ac3ddc86f6684565b65a942e04979972a7b
Add a style checker that verifies that source code doesn't contain
non-printable (control) characters. The only allowed control
characters are:
* 0x0a / \n: New line
* 0x09 / \t: Tab (the whitespace checker enforces no-tabs for C/C++ files)
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <brandon.potter@amd.com>
--HG--
extra : rebase_source : 9ba3e2971774a7b3d73cda34bbee1f19c4add746
Refactor the style checker into a Python module that can be reused by
command line tools that integrate with git. In particular:
* Create a style package in util
* Move style validators from style.py to the style/validators.py.
* Move style verifiers from style.py to the style/verifiers.py.
* Move utility functions (sort_includes, region handling,
file_types) into the style package
* Move generic code from style.py to style/style.py.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
rename : util/sort_includes.py => util/style/sort_includes.py
extra : rebase_source : ad6cf9b9a18c48350dfc7b7c77bea6c5344fb53c
The include sorter class normally yields one string per line and
relies on the caller to merge lines into a block of text separated by
newlines. However, there are cases when this isn't true. This makes
diffing using Python's difflib hard. This changeset updates the
include sorter to never do this and always yield one line at a time.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source : 154c9c7e1ebdd77e09fe5f28d0cfddc9e6c6b1eb
The Mercurial style checker extensions are currently stored in
style.py. This is not ideal since they won't work with other version
control systems. This changeset renames style.py to hgstyle.py and
adds upgrade code to scons that automatically updates the hooks in
hgrc.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nathanael Premillieu <nathananel.premillieu@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
extra : rebase_source : ee8107ef245901371b368b7c2046ecdd89e3ff4c
Remove the unsupported style.py subcommands (fixwhite, chkwhite),
which leaves the chkformat command as the only remaining
command. Since the script now only supports one command, remove the
sub-command support altogether.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nathanael Premillieu <nathananel.premillieu@arm.com>
--HG--
extra : rebase_source : 548081a5f5358064bffd941b51dd895cff1e2df8
This changeset adds an option to force the kvm-based CPUs to always
synchronize the gem5 thread context representation on entry/exit into
the kernel. This is very useful for debugging. Unfortunately, it is
also the only way to get reliable register contents when using remote
gdb functionality. The long-term solution for the latter would be to
implement a kvm-specific thread context.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Alexandru Dutu <alexandru.dutu@amd.com>
The following changes introduced substantial changes to sort_includes.py:
- hg:84b4d6af0ecc - util: Fix state leakage in ...
- hg:e2f9644a7738 - style: Update the style checker to handle new ...
Since the file didn't include a copyright header at the time, I never
added the correct ARM copyright notice. This changeset adds the
correct copyright notice.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
The style checker incorrectly includes newlines when checking lines of
code, which effectively decreases the column limit by 1. This
changeset strips the newline character from before calling line
checkers.
Change-Id: I0a8c7707ece57d782d11cc86db4b8064db291ce0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Refactor the TLB and page table walker test interface to use a dynamic
registration mechanism. Instead of patching a couple of empty methods
to wire up a TLB tester, this change allows such testers to register
themselves using the setTestInterface() method.
