1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.
src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
add the periodicity of checkpointing back into the code.
to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.
--HG--
extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
And small other tweaks to snooping coherence.
src/mem/cache/base_cache.hh:
Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
Add the function to create an atomic response to a given request
--HG--
extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache
src/mem/bus.cc:
Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
Support range changes for snoops
Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
Only access the cache if it wasn't satisfied by cache->cache transfer
Handle snoop phases (detect block, then snoop)
Fix functional access to work properly (still need to fix snoop path for functional accesses)
--HG--
extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
accessed during the construction of another static global
object because there are no guarantees on ordering of
construction, so stick the static global into a function
as a static local and return a reference to the variable.
This fixes the exit callback stuff on my Mac.
--HG--
extra : convert_revision : 63a3844d0b5ee18e2011f1bc7ca7bb703284da94
src/arch/alpha/isa_traits.hh:
This got changed to the wrong version by accident.
src/cpu/base.cc:
Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
Switch out updates from the version of m5 I have. Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
Use proper method to get flags. Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
Support profiling.
src/cpu/ozone/cpu.hh:
Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
Get flags correctly.
src/cpu/ozone/thread_state.hh:
Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext.
--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
setup is correct and provide meeaningful error messages when it's not.
Also fix for building on Cygwin where python lib is in /bin and not /lib.
--HG--
extra : convert_revision : 7a29ba17463de60c72b3d8b04e4c4f81fc64bf61
cpu/ozone/cpu_impl.hh:
Be sure to update rename tables.
cpu/ozone/front_end_impl.hh:
Handle serialize instructions slightly differently. This allows front end to continue even if back end hasn't processed it yet.
cpu/ozone/lw_back_end_impl.hh:
Handle stores with faults properly.
cpu/ozone/lw_lsq.hh:
Handle committed stores properly.
cpu/ozone/lw_lsq_impl.hh:
Handle uncacheable loads properly.
--HG--
extra : convert_revision : 093edc2eee890139a9962c97c938575e6d313f09
cpu/base.cc:
Have output message regardless of build.
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
Be sure to include all parameters.
cpu/o3/cpu.cc:
IEW also needs to switch out.
cpu/o3/iew_impl.hh:
Handle stores with faults properly.
cpu/o3/inst_queue_impl.hh:
Switch out properly, handle squashing properly.
cpu/o3/lsq_unit_impl.hh:
Minor fixes.
cpu/o3/mem_dep_unit_impl.hh:
Make sure mem dep unit is switched out properly.
cpu/o3/rename_impl.hh:
Switch out fix.
--HG--
extra : convert_revision : b94deb83f724225c01166c84a1b3fdd3543cbe9a
src/SConscript:
add intel nic to sconscript
src/dev/pcidev.cc:
fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
Move config_latency into pci where it belogs
--HG--
extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
util/statetrace/Makefile:
Makefile to build statetrace. Targets are:
statetrace: alias to build using the "native" compiler
statetrace-native: use the native compiler
statetrace-sparc: use the sparc cross compiler
I'll make this a little more fancy and capable later.
util/statetrace/arch/tracechild_i386.cc:
Implementation of i386 support
util/statetrace/arch/tracechild_i386.hh:
Declaration of i386 support
util/statetrace/arch/tracechild_sparc.cc:
implementation of SPARC support
util/statetrace/arch/tracechild_sparc.hh:
declaration of SPARC support
util/statetrace/printer.cc:
Implementation of the "Printer" objects which parse and output the state of the process after each instruction. There are currently two types of printers, nested ones and register ones. These are called NestingPrinter and RegPrinter respectively.
util/statetrace/printer.hh:
Declaration of "Printer" objects
util/statetrace/refcnt.hh:
This is copied from m5. I should use the one already in the tree, but I'll do that later.
util/statetrace/regstate.hh:
Interface for accessing registers.
util/statetrace/statetrace.cc:
Main file with argument parsing and the "main" function which contains the tracing loop.
util/statetrace/tracechild.cc:
Implementation of the base tracechild class.
util/statetrace/tracechild.hh:
Declaration of the base tracechild class.
util/statetrace/tracechild_arch.cc:
This file hooks in support for the appropriate architecture. Just the implementation is brought in, since the main program should ideally not have to know anything at all about an architecture other than it's interface.
util/statetrace/x86.format:
An example output template for x86. A few example SPARC templates will be added later.
--HG--
extra : convert_revision : 7c8bf8230907aba42ed1e707b9ca2d6da0d4e6d4
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.
--HG--
extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
Includes support for printing readable VectorPort and Proxy names
(via __str__).
--HG--
extra : convert_revision : c48534a498b3036fe6ac45ff1606656546c79afb
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
Some tweaking to deal with mutually recursive imports.
--HG--
rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
src/python/m5/config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
--HG--
extra : convert_revision : cb25ee1f4f77d1902511ee9aa766403733dd8841
