Commit graph

17 commits

Author SHA1 Message Date
Gabe Black
872bbdfc33 Hand merge. Stuff probably doesn't compile.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
2006-03-09 18:35:28 -05:00
Nathan Binkert
7546fabe68 Ethernet devices have an RSS option to tell the driver to
use Receive side scaling

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
    add support for setting the RSS flag to notify the driver
    to use RSS

--HG--
extra : convert_revision : 5f0c11668ae976634b3bf0caad669a9464a4c041
2006-03-03 14:17:48 -05:00
Steve Reinhardt
22504f8b48 More progress toward actually running a program.
See configs/test.py for test config (using simple
binary in my home directory on zizzer).

base/chunk_generator.hh:
    Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
    Fix roundDown to take integer alignments.
cpu/base.cc:
    Register exec contexts regardless of state (not sure why
    this check was in here in the first place).
mem/physical.cc:
    Add breaks to switch.
python/m5/objects/BaseCPU.py:
    Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
    HierParams is gone.
python/m5/objects/PhysicalMemory.py:
    mmu param is full-system only.
sim/process.cc:
    Stack mapping request must be page-aligned and page-sized.
    Don't delete objFile object in create since we are counting
    on it being around for startup().

--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
2006-03-01 18:45:50 -05:00
Nathan Binkert
3a0102536b Get rid of the code that delays PIO write accesses
until the cache access occurs.  The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
    get rid of pio_delay write and the associated code to move
    the write to the cache access function
dev/sinicreg.hh:
    no more write delays
python/m5/objects/Ethernet.py:
    get rid of pio_delay write

--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
2006-02-20 23:41:50 -05:00
Nathan Binkert
47ff0af17e Virtualize sinic
separate the rx thread and tx thread and get rid of the dedicated flag.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
    dedicated flag goes away, we have new individual flags for
    rx thread and tx thread
dev/sinic.cc:
    Virtualize sinic
    - The io registers are replicated many times in memory, allowing the NIC to
    differentiate among several virtual interfaces.
    - On the TX side, this allows multiple CPUs to initiate transmits at the same
    time without locking in the software.  If a partial packet is transmitted,
    then the state machine blocks waiting for that virtual interface to complete
    its packet.  Then the state machine will move on to the next virtual
    interface.  The commands are kept in fifo order.
    - On the RX side, multiple partial transmits can be simultaneously done.
    Though a packet does not deallocate its fifo space until all preceeding
    packets in the fifo are deallocated.  To enable multiple receives, it
    is necessary for each virtual nic to keep its own information about its
    progress through the state machine.
dev/sinic.hh:
    Virtualize sinic
    Receive state must be virtualized since we allow the receipt of packets in
    parallel.
dev/sinicreg.hh:
    Virtualize sinic
    separate rx thread and tx thread
    create a soft interrupt and add a command to trigger it.
    pad out the reserved bits in the RxDone and TxDone regs

--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
2005-11-25 13:33:36 -05:00
Nathan Binkert
f806a25c9e add support for delaying pio writes until the cache access occurs
dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
2005-11-21 23:43:15 -05:00
Ali Saidi
3b66cb49ec Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
extra : convert_revision : 3cc23080d19cc464a8ba7c1c93b6e5d45af7d463
2005-11-02 14:56:18 -05:00
Ali Saidi
15ccd16fd8 Add Mem/Ethernet latency variability parameter
python/m5/objects/Ethernet.py:
    Add Latency Variability Parameter

--HG--
extra : convert_revision : db5431cccffea8c7247d0f72e4770d4d58bd25aa
2005-11-02 14:44:42 -05:00
Nathan Binkert
b7b8ffa7b7 Major changes to sinic device model. Rearrage read/write, better
interrupts.

dev/sinic.cc:
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    Includes RxDone, RxWait, TxDone, and TxWait
    - Use the new register information accessor functions to grab
    validity and size information for the read and write functions
    - read all registers directly from the register space by offset
    and size, not by actual name (less code)
    - The side effect of reading the interrupt status (clearing it) now
    happens outside the actual chunk of code where the value is loaded.
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - When RxData or TxData are written, their busy flag is set to
    indicate that they have an outstanding transaction.
    - The RxHigh and TxLow interrupts are special, they only interrupt
    if the rxEmpty or txFull limits were hit
    - Move reset to the command register
    - Update more registers on reset, clear rxEmpty and txFull
    - Data dumps only happen if EthernetData trace flag set
    - When a DMA completes, kick the other engine if it was waiting
    - implement all of the new interrupts
    - serialize the new stuff
dev/sinic.hh:
    - Put all registers with their proper size and alignment into
    the regs struct so that we can copy multiple at a time.
    - Provide accessor functions for accessing the registers with
    different sizes.
    - Flags to track when the rx fifo hit empty and the tx fifo became
    full.  These flags are used to determine what to do when below
    the watermarks, and are reset when crossing the watermark.
    - the txDmaEvent should actually trigger the txDmaDone function
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    - add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
    Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
    rename XxThreshold to XxFifoMark
    Move Reset to the Command register
    Add Thread to the Config register
    New interrupts, better names
    More info in RxDone and TxDone
    Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
    Both sinic and nsgige have the dedicated thread
    Add a parameter to configure the maximum number for receive
    packets per interrupt

--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-21 20:28:21 -04:00
Nathan Binkert
2badc0113c Shuffle around device names to make things easier to read.
Create EtherDevBase which both Sinic and NSGigE derive from
bump fifos
drop rx max copy size to 1514 bytes to be friendlier with linux
default interrupt delay is 10us

dev/ns_gige.cc:
    Shuffle around parameters to make it easier to find stuff
dev/sinic.cc:
    Shuffle around parameters to make it easier to find stuff
    rename cycleTime -> clock
dev/sinic.hh:
    rename cycleTime -> clock

--HG--
extra : convert_revision : a673bee875e50d083098991aea20972fa8d5b5c7
2005-10-18 22:05:05 -04:00
Nathan Binkert
4f43bc65ea use the dedicated flag, no more exposing the m5reg directly
dev/ns_gige.cc:
    stop exposing the m5reg to the configuration stuff and build it
    based on exposed flags.  Expose dedicated now.
dev/ns_gige.hh:
    goodbye m5reg hello dedicated
dev/ns_gige_reg.h:
    Flags for the M5REG

--HG--
extra : convert_revision : 11134fe67cdf5291caacf9b3041739c437b983e3
2005-10-18 21:01:05 -04:00
Nathan Binkert
f88d7c7456 Fix the EtherDump parameters
dev/etherdump.cc:
    no default parameters anymore they should be in python
python/m5/objects/Ethernet.py:
    move the maxlen parameter for EtherDump into python

--HG--
extra : convert_revision : a796353a68907dfeb22059cd3ad536e6e8f60998
2005-09-17 10:47:16 -04:00
Nathan Binkert
c4029ecb30 Implement a state machine clock that acutally limits how fast
the nsgige state machine can run. The frequency is of the actual
state transitions, and not the rate of what underlying
instructions might run at.

dev/ns_gige.cc:
    Implement a state machine clock that acutally limits how fast
    the state machine can run.  After each state transition, a
    variable is kept to hold the next state transition until the
    next clock.  The frequency is of the actual state transitions,
    and not the rate of what underlying instructions might run at.
dev/ns_gige.hh:
    Add back the rxKickEvent and txKickEvent events.
python/m5/objects/Ethernet.py:
    Default the state machine clock to '0ns' so the default
    behaviour doesn't change when we actually implement the
    state machine clock.

--HG--
extra : convert_revision : 2db1943dee4e91ea75aaee6a91e88f27f01a09dd
2005-06-27 17:02:40 -04:00
Nathan Binkert
3e5e3e2d28 make all of the turbolaser stuff only compile if ALPHA_TLASER
is defined.

build/SConstruct:
    Default ALPHA_TLASER to false
dev/uart8250.cc:
    fix paths

--HG--
extra : convert_revision : 3616b5b4b9060860a73568a4ed4f1e8eb991938f
2005-06-05 01:24:17 -04:00
Nathan Binkert
0ee75f27b8 Fix-up some config issues
python/m5/config.py:
    Make NetworkBandwidth and MemoryBandwidth work
python/m5/objects/Ethernet.py:
    Make 1Gbps default for ethernet

--HG--
extra : convert_revision : 59e62f7e62624356ae8d7304598617f60667f040
2005-06-02 11:19:01 -04:00
Steve Reinhardt
8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
Steve Reinhardt
aad02f8088 Major cleanup of python config code.
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
2005-05-29 01:14:50 -04:00
Renamed from python/m5/objects/Ethernet.mpy (Browse further)