8031cd93b5
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
Minor tweaks on Frequency/Latency:
- added new Clock param type to avoid ambiguities
- factored out init code into getLatency()
- made RootFrequency *not* a subclass of Frequency so it
can't be directly assigned to a Frequency paremeter
--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
123 lines
4.9 KiB
Python
123 lines
4.9 KiB
Python
from m5 import *
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from Device import DmaDevice
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from Pci import PciDevice
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class EtherInt(SimObject):
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type = 'EtherInt'
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abstract = True
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peer = Param.EtherInt(NULL, "peer interface")
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class EtherLink(SimObject):
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type = 'EtherLink'
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int1 = Param.EtherInt("interface 1")
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int2 = Param.EtherInt("interface 2")
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delay = Param.Latency('0us', "packet transmit delay")
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speed = Param.NetworkBandwidth('100Mbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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class EtherBus(SimObject):
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type = 'EtherBus'
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loopback = Param.Bool(True, "send packet back to the sending interface")
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dump = Param.EtherDump(NULL, "dump object")
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speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
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class EtherTap(EtherInt):
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type = 'EtherTap'
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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port = Param.UInt16(3500, "tap port")
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class EtherDump(SimObject):
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type = 'EtherDump'
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file = Param.String("dump file")
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class EtherDev(DmaDevice):
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type = 'EtherDev'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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intr_delay = Param.Latency('0us', "Interrupt Delay")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
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tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
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class NSGigE(PciDevice):
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type = 'NSGigE'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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clock = Param.Clock('100MHz', "State machine processor frequency")
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
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tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
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m5reg = Param.UInt32(0, "Register for m5 usage")
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intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
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class EtherDevInt(EtherInt):
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type = 'EtherDevInt'
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device = Param.EtherDev("Ethernet device of this interface")
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class NSGigEInt(EtherInt):
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type = 'NSGigEInt'
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device = Param.NSGigE("Ethernet device of this interface")
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class Sinic(PciDevice):
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type = 'Sinic'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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clock = Param.Clock('100MHz', "State machine processor frequency")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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rx_max_copy = Param.MemorySize('16kB', "rx max copy")
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tx_max_copy = Param.MemorySize('16kB', "tx max copy")
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rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo")
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tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo")
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rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
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tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
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intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
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class SinicInt(EtherInt):
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type = 'SinicInt'
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device = Param.Sinic("Ethernet device of this interface")
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