8031cd93b5
Fix description for Bus clock_ratio (no longer a ratio). Add Clock param type (generic Frequency or Latency). cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/beta_cpu/alpha_full_cpu_builder.cc: cpu/simple_cpu/simple_cpu.cc: dev/ide_ctrl.cc: dev/ns_gige.cc: dev/ns_gige.hh: dev/pciconfigall.cc: dev/sinic.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/Ethernet.py: python/m5/objects/Root.py: sim/universe.cc: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). python/m5/config.py: Minor tweaks on Frequency/Latency: - added new Clock param type to avoid ambiguities - factored out init code into getLatency() - made RootFrequency *not* a subclass of Frequency so it can't be directly assigned to a Frequency paremeter --HG-- extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506 |
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.. | ||
AlphaConsole.py | ||
AlphaFullCPU.py | ||
AlphaTLB.py | ||
BadDevice.py | ||
BaseCache.py | ||
BaseCPU.py | ||
BaseSystem.py | ||
Bus.py | ||
CoherenceProtocol.py | ||
Device.py | ||
DiskImage.py | ||
Ethernet.py | ||
Ide.py | ||
IntrControl.py | ||
MemTest.py | ||
Pci.py | ||
PhysicalMemory.py | ||
Platform.py | ||
Process.py | ||
Repl.py | ||
Root.py | ||
SimConsole.py | ||
SimpleDisk.py | ||
Tsunami.py | ||
Uart.py |