8031cd93b5
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
Minor tweaks on Frequency/Latency:
- added new Clock param type to avoid ambiguities
- factored out init code into getLatency()
- made RootFrequency *not* a subclass of Frequency so it
can't be directly assigned to a Frequency paremeter
--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
20 lines
842 B
Python
20 lines
842 B
Python
from m5 import *
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from HierParams import HierParams
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from Serialize import Serialize
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from Statistics import Statistics
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from Trace import Trace
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class Root(SimObject):
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type = 'Root'
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clock = Param.RootClock('200MHz', "tick frequency")
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output_file = Param.String('cout', "file to dump simulator output to")
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checkpoint = Param.String('', "checkpoint file to load")
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# hier = Param.HierParams(HierParams(do_data = False, do_events = True),
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# "shared memory hierarchy parameters")
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# stats = Param.Statistics(Statistics(), "statistics object")
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# trace = Param.Trace(Trace(), "trace object")
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# serialize = Param.Serialize(Serialize(), "checkpoint generation options")
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hier = HierParams(do_data = False, do_events = True)
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stats = Statistics()
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trace = Trace()
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serialize = Serialize()
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