Commit graph

4387 commits

Author SHA1 Message Date
Ali Saidi
ccd67ce44f Rearange tlb code to remove some duplicate
Sparc error register should return ull(0) since it's 64 bits
Fix PS1 pointer creation to use the ps1 page size rather than ps0

--HG--
extra : convert_revision : fb4ef4b90270c8db676ffe53578acfa3c244526e
2007-01-20 12:37:02 -05:00
Ali Saidi
6e0f1c6062 Spill and Fill handlers are actually n*4 + the start address
--HG--
extra : convert_revision : a42f01a84e4b7ba9e6029df50e1612d410a8ba22
2007-01-20 12:34:00 -05:00
Lisa Hsu
01c959aeaf Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
2007-01-19 21:34:21 -05:00
Lisa Hsu
f1aeaf7ceb some hstick and hintp changes.
src/arch/sparc/interrupts.hh:
    condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
    implement HINTP
src/arch/sparc/ua2005.cc:
    don't post interrupt unless it is enabled.

--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
2007-01-19 21:33:36 -05:00
Ali Saidi
ae0d8d1681 Allow ASI_LDTX_REAL
--HG--
extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
2007-01-17 18:36:12 -05:00
Ali Saidi
c8a2d602b1 do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many
fix for lookup table to keep it consistant with tlb on a replace of a specific entry

--HG--
extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
2007-01-17 17:59:22 -05:00
Ali Saidi
8173a05eaf Implement reading writing of sync fault status register and address register
--HG--
extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
2007-01-17 13:09:26 -05:00
Ali Saidi
64528df38d In the case that we generate a fault (e.g. a tlb miss) on a microcoded instruction set curMacroStaticInst to null
This way we'll jump immediately to the handler

--HG--
extra : convert_revision : 36218d3a5c2342337e66e1229ea2219533efd41e
2007-01-16 19:12:33 -05:00
Ali Saidi
8d75e4ac3f Don't add symbols for loaded files to symbol table since they are pretty much meaningless with all the copying that goes on
--HG--
extra : convert_revision : 4d2c1bb72c0344d78d9c3d5958feb3de247102a0
2007-01-16 19:09:27 -05:00
Ali Saidi
d6c92cdb3c Fix legion lock code a bit so that if we jump out of a micro coded instruction (because of a fault on the first op) we don't lose sync with legion
Only print TLB if there is a tlb difference

--HG--
extra : convert_revision : f3baf667ca466d6b8efcaccd186ecec14498229d
2007-01-16 19:08:21 -05:00
Ali Saidi
0584d5bd6c In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
--HG--
extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423
2007-01-16 19:06:33 -05:00
Ali Saidi
ecfd628ecd Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last

src/arch/sparc/isa/decoder.isa:
    Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
    set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
    Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
    Add IsFirstMicroop flag to static insts

--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
2007-01-16 19:06:05 -05:00
Lisa Hsu
5c9cbdbb45 Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge between ali and me.

--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
2007-01-11 09:48:15 -05:00
Lisa Hsu
42535f5f53 ua2005.cc:
formatting/indentation for case statements

src/arch/sparc/ua2005.cc:
    formatting/indentation for case statements

--HG--
extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
2007-01-11 09:41:34 -05:00
Lisa Hsu
9f75c1c58f ua2005.cc:
i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

src/arch/sparc/ua2005.cc:
    i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
2007-01-11 09:29:03 -05:00
Lisa Hsu
d939060ec6 Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time.
--HG--
extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
2007-01-11 09:18:31 -05:00
Ali Saidi
9d04510869 bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
    some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
    fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
    legion always returns du and dl set, so we need to emulate that for now at least

--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
2007-01-10 22:19:13 -05:00
Ali Saidi
28a83c6d1c quiet/remove some warnings
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis

src/arch/sparc/miscregfile.cc:
    get rid of some warnings
    fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
    implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
    make warning less verbose

--HG--
extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
2007-01-09 22:20:38 -05:00
Ali Saidi
7933aade85 add memory mapped disk device
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
    add configuration for memory mapped disk
src/dev/sparc/SConscript:
    add memory mapped disk to sconscript

--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
2007-01-09 22:16:49 -05:00
Lisa Hsu
0d7282d7ab pagetable.hh:
small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile

src/arch/alpha/interrupts.hh:
    small fix for alpha compile
src/arch/alpha/pagetable.hh:
    small fix so ALPHA_FS will build on macs

--HG--
extra : convert_revision : 5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
2007-01-08 20:50:45 -05:00
Lisa Hsu
032ea9b2db the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh:
    fill in how we do interrupts on sparc a little bit.

    1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
    2) fill in getInterrupts() a little bit.

    also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
    1) update formatting
    2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
    overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.

--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08 18:18:28 -05:00
Lisa Hsu
b45219e7ae some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion.
src/arch/sparc/faults.cc:
    1) s/Resumeable/Resumable/gc
    2) s/if(/if (/gc
    3) keep variables lowercase
    4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv).
src/arch/sparc/faults.hh:
    s/Resumeable/Resumable/
src/arch/sparc/isa_traits.hh:
    This is unused and unnecessary.
src/arch/sparc/miscregfile.hh:
    add bitfield masks for some important ASRs (HPSTATE, PSTATE).

--HG--
extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
2007-01-08 18:07:17 -05:00
Ali Saidi
a8b2d66661 change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff
at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.

--HG--
extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042
2007-01-08 17:11:10 -05:00
Ali Saidi
2f4239a685 fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still
src/arch/sparc/miscregfile.cc:
    fix softint and fprs in miscregfile

--HG--
extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
2007-01-08 17:09:48 -05:00
Ali Saidi
4a8078192d set the softint appropriately on an timer compare interrupt
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly

src/arch/sparc/faults.cc:
    there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
    correct protection defines
src/arch/sparc/ua2005.cc:
    set the softint appropriately on an timer compare interrupt

--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
2007-01-05 15:04:17 -05:00
Ali Saidi
b0f11f8f81 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : e8ac13e1222796ab362fabb9b19694682538da29
2007-01-04 20:22:56 -05:00
Ali Saidi
b46aa88435 Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time
turn warnings into dprintfs

src/arch/sparc/miscregfile.cc:
    turn dprintfn into dprintfs

--HG--
extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
2007-01-04 20:22:45 -05:00
Nathan Binkert
e6b4fed75d set __name__ in the root m5 script to __m5_main__ so we can
tell if the script is run from m5 as the m5 script

--HG--
extra : convert_revision : 06f646cbb8c82444ef345115aa49324a4d3a2c9f
2007-01-03 10:16:22 -08:00
Nathan Binkert
e9a395c2ce Formatting
--HG--
extra : convert_revision : bf1eae73995f772a4343c8ebcb254818eeb5d949
2007-01-03 10:13:45 -08:00
Nathan Binkert
fc45d42d01 Add 'Time' as a parameter type that can accept various
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit

--HG--
extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
2007-01-03 10:12:55 -08:00
Gabe Black
8840ebcb00 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2007-01-03 00:52:30 -05:00
Kevin Lim
7d7f3d0e99 Fix up previous commit to proper logic.
src/cpu/o3/commit_impl.hh:
    Oops, changed the logic a little bit.  Fix it up to how it used to be.

--HG--
extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
2006-12-30 13:21:25 -05:00
Nathan Binkert
f6aa2ed47b Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/m5/incoming

--HG--
extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
2006-12-29 16:58:08 -08:00
Nathan Binkert
81e0ac3000 Formatting
--HG--
extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
2006-12-29 16:57:45 -08:00
Gabe Black
a0e8aa6737 Fixes to get non-delay slot ISAs (Alpha) working again, and pulling some debug output out of ifdefs.
--HG--
extra : convert_revision : 29d0969e2d3e809aac32262ba20907e6e4ef1a42
2006-12-28 14:35:31 -05:00
Gabe Black
3f2b25d997 Phased out DelaySlotInfo.
--HG--
extra : convert_revision : ab48db10caf38137300da63078aa9360f46b9631
2006-12-28 14:33:45 -05:00
Gabe Black
d24f60788f Some fixes for decode stage branches without delay slots. This will need some work to be compatible with delay slots too. Also changed some direct variable uses to use an accessor function.
--HG--
extra : convert_revision : b291292600e9d3e7e4a8255daf54342b736c7e35
2006-12-28 14:32:41 -05:00
Gabe Black
15df0a27bb Make sure the value of PC is actually updated now that the instruction target isn't set explicitly.
--HG--
extra : convert_revision : 4c00a219ac1d82abea78e4e8d70f529a435fdfe2
2006-12-28 14:29:17 -05:00
Gabe Black
b642ad00eb Implement a stub nnpc for alpha that is read only as npc+4.
--HG--
extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-28 14:27:45 -05:00
Gabe Black
9ca6efdb60 Fixed NumMiscArchRegs. This is still a magic number, and it should be set automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti.
--HG--
extra : convert_revision : eb640c9ef10a188b96f6a079f91abc8f67b9d38c
2006-12-28 14:23:30 -05:00
Ali Saidi
b48a8fb347 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27 14:38:22 -05:00
Ali Saidi
ba14d6d0e1 Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48

src/arch/sparc/tlb.cc:
    Bug fixes in the TLB
    Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
    Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
    itb should be 64 entries too

--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-27 14:38:07 -05:00
Ali Saidi
ff88f3b13a Compare legion and m5 tlbs for differences
Only print faults instructions that aren't traps or faulting loads

src/cpu/exetrace.cc:
    Compare the legion and m5 tlbs and printout any differences
    Only show differences if the instruction isn't a trap and isn't a memory
    operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
    update the m5<->legion interface to add tlb data

--HG--
extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
2006-12-27 14:35:23 -05:00
Ali Saidi
b6dc902f6a Change MemoryAccess dprintfs to print the data as well
--HG--
extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
2006-12-27 14:32:26 -05:00
Nathan Binkert
9e90bfafb5 No need to use NULL, just use 0
The result of operator= cannot be an l-value

--HG--
extra : convert_revision : df97a57f466e3498bd5a29638cb9912c7f3e1bd4
2006-12-27 10:52:25 -08:00
Kevin Lim
0bd7518480 Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
--HG--
extra : convert_revision : 5c334ec806305451b3883c7fd0ed9cd695c038bc
2006-12-26 01:43:18 -05:00
Nathan Binkert
2d029fe584 Make sure that all of the bits in the result are set
to some value.

--HG--
extra : convert_revision : 1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
2006-12-24 15:15:12 -08:00
Nathan Binkert
e68a87e7fa remove some output formatting stuff that we don't use
--HG--
extra : convert_revision : 367917499d3d7aebd0a91dad28c915bc85def624
2006-12-24 14:06:56 -08:00
Nathan Binkert
91ffe811a3 Add options for setting the kernel to run and the
script to run

--HG--
extra : convert_revision : 32ad8e08ca74edf042d8606ca4876cbe1193e932
2006-12-22 21:51:19 -08:00
Nathan Binkert
139dcbe088 Fix copyright
--HG--
extra : convert_revision : 8ad7824885a5c4da80175c47ba5288aab55b06ca
2006-12-21 22:41:08 -08:00