Commit graph

22 commits

Author SHA1 Message Date
Steve Reinhardt
935ba67b4f Get basic full-system working with AtomicSimpleCPU.
SConscript:
    Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
    Fix paths.
configs/test/fs.py:
    SimpleCPU -> AtomicSimpleCPU
    Fix vmlinux path
cpu/simple/atomic.cc:
    Fix suspendContext() so quiesce works.
    Don't forget to checkForInterrupts().
cpu/simple/base.cc:
    Minor fix to interrupt check code.
dev/ide_disk.hh:
    Don't declare regStats() in header since it's not in
    .cc file anymore (will need to add it back in when
    stats are added back).
dev/io_device.cc:
    Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
    Set PCI config packet result to Success.
python/m5/objects/Root.py:
    Add debug object to Root so things like break_cycles
    can be set from command line.

--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
2006-05-17 22:08:44 -04:00
Steve Reinhardt
309e1d8193 Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
2006-05-16 17:36:50 -04:00
Korey Sewell
0930024b88 Minor changes for FP ... MIPS now works for floating-point programs...
Now we are to the point where more benchmarks and instruction-coverage
is necessary to totally verify/validate correct operation across
all MIPS instructions

arch/mips/isa_traits.hh:
    fix for reading double values ... must rearrange bits before using void* to read double.
configs/test/hello_mips:
    real hello world MIPS binary

--HG--
extra : convert_revision : 153de1f8a830882c6972bd0bdb56da818f614def
2006-05-07 14:09:19 -04:00
Korey Sewell
de8eba6891 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : c48a8857f5a520ff8061eb3d8f08dcd43661e68c
2006-05-04 21:10:51 -04:00
Korey Sewell
97429d8eee Redo the FloatRegFile using unsigned integers
Edit the convert_and_round function which access FloatRegFile

arch/isa_parser.py:
    recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
    Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
    bit manipulation ourselves. We can just concern ourselves with values.

    Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
    float debug statement
arch/mips/isa_traits.cc:
    add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
    Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
    basic FP program
cpu/simple/cpu.hh:
    spacing

--HG--
extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
2006-05-02 20:05:16 -04:00
Ali Saidi
ca8a659394 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : d6f7c4dd146613eeba39249f2d916a77108bc8c1
2006-04-28 15:41:22 -04:00
Ali Saidi
79170b1be5 random mix of tidbits
configs/test/fs.py:
    update fs.py to use a bus bridge
cpu/simple/cpu.hh:
    cpu should just return that it doesn't snoop any address ranges
python/m5/objects/System.py:
    move boot_osflags to system

--HG--
extra : convert_revision : b4256df7eada7e65b69513361de8bffc3fdd680b
2006-04-28 15:40:45 -04:00
Gabe Black
20c8553787 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

cpu/simple/cpu.cc:
    Hand merged

--HG--
extra : convert_revision : 68414730c23d41c30cfb7bcfa604029a5fc8622c
2006-04-28 14:03:42 -04:00
Gabe Black
25bf3125da Changed the hello_sparc executable back to the cross compiled one
--HG--
extra : convert_revision : 565f75f76dd26ca0e25de4c89d1597a9f39483fd
2006-04-28 13:11:32 -04:00
Ali Saidi
8f8d09538f Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-24 19:31:50 -04:00
Ali Saidi
6dc3b2fa39 make ide disk work for newmem
SConscript:
    compile ide devices
base/chunk_generator.hh:
    add another parameter to the chuck generator called complete() which
    returns the number of bytes transfered so far. Very useful for
    adding to a pointer.
configs/test/fs.py:
    Add ide disk to fs test configuration
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
    update for new memory system
mem/bus.cc:
    support devices that return multiple ranges
    remove old ranges before using new info
mem/packet.hh:
    make senderstate void* per steve's request that we use every
    construct possible in C++
mem/physical.cc:
    have memory stamp the packet with the time.
mem/physical.hh:
    actually set the memory latency variable
python/m5/objects/Device.py:
    Add DmaDevice
python/m5/objects/Ide.py:
    Ide disk no longer has a physmem pointer
python/m5/objects/Pci.py:
    update pci device for newmem
python/m5/objects/PhysicalMemory.py:
    add latency parameter for physical memory
sim/byteswap.hh:
    use fast architecture dependent byteswap calls if they exist

--HG--
extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 17:14:30 -04:00
Korey Sewell
200205aa85 update Hello World binary for mips... the old one did not have a newline
--HG--
extra : convert_revision : f015cac39e42e11b1a56bbd1c5cf07403eb8f2da
2006-04-13 17:40:16 -04:00
Ali Saidi
81a735a716 fs now gets to the point where it would really like a filesystem.
Time to make the ide device work

arch/alpha/system.cc:
    write the machine type and rev in the correct place
cpu/simple/cpu.cc:
    reset the packet structure every time it's reused... wow the
    simple cpu code  for talking to memory is getting horrible.
dev/alpha_console.cc:
    move the setAlphaAccess to startup() to make sure that the console
    binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
    fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
    More verbose bus tracing
mem/packet.hh:
    Add a constructor to packet to set the result to unknown and a reset
    method in the case it's being reused
mem/vport.hh:
    don't need are own read/write methods since the base functional port
    ones call writeBlob readBlob which do the translation for us

--HG--
extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 17:46:25 -04:00
Ali Saidi
6a7108897b a sparc binary that can be debugged
--HG--
extra : convert_revision : cb021c1e704b5771e0f86e794b7e59f8a4b96856
2006-04-06 18:32:10 -04:00
Gabe Black
6d8d6d15cd Fixed up the isa description. Also added some capability to the isa_parser in the InstObjParams constructor.
arch/isa_parser.py:
    Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
    Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
    Added SPARC traceflag
configs/test/hello_sparc:
    Recompiled without -mflat
cpu/cpu_exec_context.cc:
    Used the regfile clear function rather than memsetting to 0.

--HG--
extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
2006-04-06 14:52:44 -04:00
Gabe Black
5c79eb0410 Fixes to SPARC for syscall emulation mode.
arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
    Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
    Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
    Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
    Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
    A test program for SPARC which prints "Hello World!"

--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
2006-03-31 20:31:53 -05:00
Ali Saidi
3dcb589ea4 update for connector magic
--HG--
extra : convert_revision : 111af292373edebcd106938e76610f9ac4a6ce58
2006-03-29 17:39:20 -05:00
Ali Saidi
4973a16b34 update for objects having a bus
--HG--
extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b
2006-03-25 18:34:50 -05:00
Korey Sewell
77a2f97c35 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips

--HG--
extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
2006-03-15 23:38:55 -05:00
Ali Saidi
97e424982a add translations for new sections that are mmapped or when the brk
is changed
Add a default machine width parameter
Arch based live processes

arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
    Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
    Add a default machine width parameter
mem/port.hh:
    gcc 4 really wants  a virtual destructor
sim/byteswap.hh:
    remove the comment around long and unsigned long even though uint32_t
    and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    add translations for new sections that are mmapped or when the brk
    is changed

--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
2006-03-15 17:04:50 -05:00
Korey Sewell
e2b558112b add mips simple test in config directory
configs/test/hello_mips:
    hello world mips binary

--HG--
extra : convert_revision : 5a495e1bfb1cbddc0879f8e80c02bd7435a02acb
2006-03-15 16:29:18 -05:00
Steve Reinhardt
e3d96aa889 Compiles now (with CPU_MODELS=SimpleCPU), but hangs
on execution.

configs/test/test.py:
    Move test binary out of m5-test, don't depend on
    m5-test/Benchmarks.
python/m5/objects/System.py:
    Split out full-system-only parameters (lost in merge).
sim/system.cc:
    Need to be able to instantiate System directly in SE mode
    (lost in merge).
sim/system.hh:
    A few more functions here are FS-only.
configs/test/hello:
    Add in binary.

--HG--
rename : configs/test.py => configs/test/test.py
extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395
2006-03-10 10:01:29 -05:00