Commit graph

3860 commits

Author SHA1 Message Date
Gabe Black
729dbb60e9 Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
    Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.

--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
2006-12-17 11:15:37 -05:00
Gabe Black
91b56d03fc Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : c8718b3df72b8c951c24742e8ce517a93bc23fe9
2006-12-16 12:55:55 -05:00
Gabe Black
c9f18981f9 Merge zizzer:/bk/sparcfs/
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : 2764b356ef01d1fcb6ed272e4ef96179cd651d4e
2006-12-16 12:55:15 -05:00
Gabe Black
b9d069167c Support for twin loads.
src/arch/sparc/isa/decoder.isa:
    Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
    Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
    Comment explaining twin load operands.

--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
2006-12-16 12:54:28 -05:00
Gabe Black
fe73760388 Compiler error fix.
--HG--
extra : convert_revision : 39e2638a10bf3e821e8f3d4d8c664008c98fc921
2006-12-16 12:53:01 -05:00
Lisa Hsu
4da37bcd1b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
2006-12-15 18:07:39 -05:00
Lisa Hsu
956e673c55 Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 68e9bb607fbeb1ed0ea4192411e804dc8e6ddd95
2006-12-15 18:02:23 -05:00
Lisa Hsu
385a3ff054 small change to eliminate address range overlap.
--HG--
extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
2006-12-15 17:58:20 -05:00
Lisa Hsu
551ba56ae2 little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.

src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
    Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
    pioSize indicates SIZE, not a mask

--HG--
extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
2006-12-15 17:55:47 -05:00
Lisa Hsu
991146218d Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
2006-12-15 13:27:53 -05:00
Lisa Hsu
b93b32ec33 Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
2006-12-15 13:06:37 -05:00
Lisa Hsu
573d59441e some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode

src/arch/sparc/miscregfile.cc:
    fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
    fix for build
src/cpu/exetrace.cc:
    wrap this variable between FULL_SYSTEM #ifs

--HG--
extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
2006-12-15 13:05:46 -05:00
Lisa Hsu
fbc796b347 loadstore.isa:
this privilegedString is never used

--HG--
extra : convert_revision : 5e6881d467792b670e0009cee8d5e96bc7a79a95
2006-12-15 13:01:06 -05:00
Lisa Hsu
9a4370ec3b tlb.cc:
fix namespace indentations

src/arch/alpha/tlb.cc:
    fix namespace indentations

--HG--
extra : convert_revision : 327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
2006-12-15 12:58:02 -05:00
Ali Saidi
4943d58272 Use my range_map to speed up findPort() in the bus. The snoop code could still use some work.
--HG--
extra : convert_revision : ba0a68bd378d68e4ebd80a101b965d36c8be1db9
2006-12-15 01:49:41 -05:00
Ali Saidi
5e70511bff Optimized the TLB translations with some caching
--HG--
extra : convert_revision : f79f863393f918ff9363b2c261f8c0dfec64312e
2006-12-15 01:48:09 -05:00
Ali Saidi
fa4293af33 flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff

src/arch/sparc/asi.cc:
    flesh out twinx asis
src/arch/sparc/miscregfile.cc:
    fix TICK register reads
src/arch/sparc/tlb.cc:
    reduce the number of readmiscreg accesses,
    implement tsb pointer stuff

--HG--
extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
2006-12-14 19:01:21 -05:00
Steve Reinhardt
d172e1576a Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).

--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-12-13 22:04:36 -08:00
Lisa Hsu
a10eff03a5 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 8cf3e824e4892249b12ed0fd92bb310748b18fa2
2006-12-13 17:52:24 -05:00
Lisa Hsu
98bb1c62b3 fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG--
extra : convert_revision : 4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
2006-12-13 17:51:28 -05:00
Lisa Hsu
0fa30e579e Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
2006-12-13 14:33:59 -05:00
Lisa Hsu
a983c4968c Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : c6d174716641f0b8286b8478bcb9053b3eec54e3
2006-12-13 14:33:32 -05:00
Lisa Hsu
5d42fd836b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-12 21:19:51 -05:00
Kevin Lim
bc05f5982e Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress

--HG--
extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
2006-12-12 17:55:50 -05:00
Ali Saidi
139519ef87 Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts

src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
    initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
    fix bug in tlb map code
src/base/range_map.hh:
    fix bug in rangemap code and add range_multimap
    (these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
    fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
    make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
    fix up the rangemap unit test to catch the missing case

--HG--
extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
2006-12-12 17:55:27 -05:00
Kevin Lim
c7ad7b44eb Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly.  The eon benchmark should run now.

src/cpu/o3/iew_impl.hh:
    Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).

--HG--
extra : convert_revision : b7d202dee1754539ed814f0fac59adb8c6328ee1
2006-12-12 17:35:46 -05:00
Steve Reinhardt
6c8c86f2f9 Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG--
extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-12 09:58:40 -08:00
Steve Reinhardt
a7ea4885ce If no tests are specified for regression, just build the binaries
(instead of complaining and exiting).

--HG--
extra : convert_revision : 24ac0bab7fd92d9e74c80847a667f0affcd0473d
2006-12-12 09:54:59 -08:00
Steve Reinhardt
cdc3e5bc22 Get rid of unused lock code.
--HG--
extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8
2006-12-12 02:21:03 -05:00
Kevin Lim
34924ce3b8 Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation).
--HG--
extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
2006-12-11 23:51:21 -05:00
Kevin Lim
1868c9fd7f Fix for fetch to use the icache's block size to generate proper access size.
--HG--
extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
2006-12-11 23:47:30 -05:00
Steve Reinhardt
f5a4b454c3 Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3

--HG--
extra : convert_revision : c961d1bf2acaae6807870b78f444a4a606be65cc
2006-12-10 02:05:33 -05:00
Steve Reinhardt
fecc0dbc57 Reorder CacheTags members for better cache performance.
--HG--
extra : convert_revision : cac6e9d447675805e3fcc4342e3bfdbef179fbf5
2006-12-10 02:04:53 -05:00
Steve Reinhardt
90c9ad042e Get rid of dummy 'hello world' outputs.
--HG--
extra : convert_revision : e03634b5ec6b3c855c463618968984b5df7782f9
2006-12-10 01:52:18 -05:00
Steve Reinhardt
fcb9a304b5 Delete parser reference outputs so that test will no longer be run.
Runtimes are way too long with current inputs.

--HG--
extra : convert_revision : 19323308b40fb7de00c77ee552e39ca6558804b8
2006-12-10 01:50:12 -05:00
Steve Reinhardt
7b25e4091c Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3

--HG--
extra : convert_revision : 7c78ae3298645aed2179ed4f2aa361619406f9de
2006-12-10 01:42:31 -05:00
Steve Reinhardt
96d1efe0a9 Add '-j' option directly to regress script (passed to scons).
--HG--
extra : convert_revision : 9776806b24da70b815280e47d2d5ec8674c82669
2006-12-10 01:42:16 -05:00
Steve Reinhardt
cfc6710f63 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : e1ed5c8edb95e99200b4d26317f55f71338a96df
2006-12-09 22:05:30 -08:00
Ali Saidi
4947bf276e fix lisa's hand merge
--HG--
extra : convert_revision : d25604156ae0b2cf29d92fb960b8f5d77427985b
2006-12-09 18:27:54 -05:00
Ali Saidi
2eef266c45 Merge zizzer:/bk/sparcfs
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c51fd95f7acd7cffb3ea705d7216772f0a801844
2006-12-09 18:00:49 -05:00
Ali Saidi
81a00fdcfe Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data

src/arch/sparc/faults.cc:
    Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
    allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
    fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
    cleanup/fix page table code
src/arch/sparc/tlb.cc:
    implement more mmaped iprs, fix numbered insertion  code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
    add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
    dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.

--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
2006-12-09 18:00:40 -05:00
Lisa Hsu
369e10d95a Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge

--HG--
extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
2006-12-08 15:07:26 -05:00
Lisa Hsu
da6c1f5b09 mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh:
    add in thread_context.hh to get access to tc.
    get rid of stubs that don't make sense right now.
    implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
    softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
    add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
    implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.

--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
2006-12-08 14:37:31 -05:00
Ali Saidi
ed22eb781d get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-07 18:50:33 -05:00
Steve Reinhardt
ac32645c27 Change detault regression build from opt to fast.
--HG--
extra : convert_revision : b6db0254b73a97ab6e3685c90cc9cd30ea274d4f
2006-12-07 14:41:56 -05:00
Ali Saidi
03be92f23b Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-12-06 19:25:53 -05:00
Ali Saidi
ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-06 14:29:10 -05:00
Kevin Lim
b618e733bd Fix for MIPS_SE/m5.fast compile.
--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
2006-12-06 14:23:31 -05:00
Kevin Lim
54a946604b Override default SConscript options and only build the SimpleCPUs.
--HG--
extra : convert_revision : cfcfb787d8442cb76ed766aa5bc947636f067209
2006-12-05 11:12:18 -05:00
Steve Reinhardt
2e1200e57f Merge zizzer.eecs.umich.edu:bk/newmem-cache2
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 0a7d17460f17c96fe869124f54f9c92409495003
2006-12-05 07:24:13 -08:00