Commit graph

713 commits

Author SHA1 Message Date
Gabe Black
5605079b1f ISA: Replace the translate functions in the TLBs with translateAtomic. 2009-02-25 10:15:44 -08:00
Gabe Black
a1aba01a02 CPU: Get rid of translate... functions from various interface classes. 2009-02-25 10:15:34 -08:00
Nathan Binkert
3fa9812e1d debug: Move debug_break into src/base 2009-02-23 11:48:40 -08:00
Korey Sewell
6c5afe6346 Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context 2009-02-20 11:02:48 -05:00
Steve Reinhardt
89a7fb0393 Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
2009-02-16 08:56:40 -08:00
Nathan Binkert
f255957b90 style 2009-02-10 22:19:27 -08:00
Korey Sewell
cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Korey Sewell
973d8b8b13 InOrder: Import new inorder CPU model from MIPS.
This model currently only works in MIPS_SE mode, so it will take some effort
to clean it up and make it generally useful. Hopefully people are willing to
help make that happen!
2009-02-10 15:49:29 -08:00
Korey Sewell
34a5cd8870 ExeTrace: Allow subclasses of the tracer to define their own prefix to dump 2009-02-10 15:49:29 -08:00
Korey Sewell
2d0a66cbc1 CPU: Prepare CPU models for the new in-order CPU model.
Some new functions and forward declarations are necessary to make things work
2009-02-10 15:49:29 -08:00
Gabe Black
7b58511470 CPU: Don't always reset the micro pc on faults. Let the faults handle it. 2009-02-01 00:30:54 -08:00
Gabe Black
7720968949 X86: Make sure the predecoder is cleared out for interrupts. 2009-02-01 00:04:34 -08:00
Ali Saidi
35a85a4e86 Config: Cause a fatal() when a parameter without a default value isn't set(FS #315). 2009-01-30 19:08:13 -05:00
Gabe Black
d9794784ba CPU: Add a setCPU function to the interrupt objects. 2009-01-25 20:29:03 -08:00
Nathan Binkert
f0fb3ac060 cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.
Make interrupts use the new wakeup method, and pull all of the interrupt
stuff into the cpu base class so that only the wakeup code needs to be updated.
I tried to make wakeup, wakeCPU, and the various other mechanisms for waking
and sleeping a little more sane, but I couldn't understand why the statistics
were changing the way they were.  Maybe we'll try again some day.
2009-01-24 07:27:21 -08:00
Nathan Binkert
10fc45da27 o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
Nathan Binkert
dbac448b08 thread_context: move getSystemPtr so SE mode can get to it.
There was really no reason that it should be FS only.
2009-01-19 20:36:49 -08:00
Nathan Binkert
8153790d00 SCons: centralize the Dir() workaround for newer versions of scons.
Scons bug id: 2006 M5 Bug id: 308
2009-01-13 14:17:50 -08:00
Richard Strong
81180a3bf0 This fix addresses an ill formed if statement that fails
to compile. The fix was the simple addition of another set
of parenthesis to ensure the correct condition resolution.
2009-01-11 22:45:03 -08:00
Gabe Black
b0ab5c894d Tracing: Make tracing aware of macro and micro ops. 2009-01-06 22:34:18 -08:00
Steve Reinhardt
1704ba2273 Make Alpha pseudo-insts available from SE mode. 2008-12-17 09:51:18 -08:00
Gabe Black
02cd18f536 SPARC: Truncate syscall args and return values appropriately. 2008-12-16 23:06:37 -08:00
Nathan Binkert
489e3e7381 eventq: use the flags data structure 2008-12-06 14:18:18 -08:00
Gabe Black
7a4d75bae3 CPU: Refactor read/write in the simple timing CPU. 2008-11-13 23:30:37 -08:00
Clint Smullen
1adfe5c7f3 O3CPU: Make the instcount debugging stuff per-cpu.
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
2008-11-10 11:51:18 -08:00
Nathan Binkert
9c49bc7b00 mem: update stuff for changes to Packet and Request 2008-11-10 11:51:17 -08:00
Gabe Black
846cb450f9 CPU: Make unaligned accesses work in the timing simple CPU. 2008-11-09 21:56:28 -08:00
Gabe Black
909380f3ee X86: Make the timing simple CPU handle variable length instructions. 2008-11-09 21:55:01 -08:00
Lisa Hsu
07969dbbf1 Right now a single thread cpu 1 could get assigned context Id != 1, depending
on the order in which it's registered with the system.  To make them match,
here is a little change.
2008-11-05 15:30:49 -05:00
Lisa Hsu
dd99ff23c6 get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
2008-11-04 11:35:42 -05:00
Lisa Hsu
d857faf073 Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
2008-11-02 21:57:07 -05:00
Lisa Hsu
67fda02dda Make it so that all thread contexts are registered with the System, even in
SE.  Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
2008-11-02 21:57:06 -05:00
Lisa Hsu
c55a467a06 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
2008-11-02 21:56:57 -05:00
Clint Smullen
95af120e60 CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU.
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
2008-10-27 18:18:04 -04:00
Lisa Hsu
8788d703f8 s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
comments.
2008-10-23 16:49:17 -04:00
Nathan Binkert
9836d81c2b style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
Ali Saidi
b760b99f4d O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
2008-10-20 16:22:59 -04:00
Gabe Black
809f6cb6d1 CPU: Explain why some code is commented out. 2008-10-12 23:52:02 -07:00
Gabe Black
989fa4fc0f X86: Make the MicroPC type 16 bit. 2008-10-12 20:48:24 -07:00
Gabe Black
0756dbb37a X86: Don't fetch in the simple CPU if you're in the ROM. 2008-10-12 19:32:06 -07:00
Gabe Black
f245358343 Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
Gabe Black
c9ea0b7349 CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM. 2008-10-12 16:59:55 -07:00
Gabe Black
2736086d7c CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
Gabe Black
d0a43ce2b2 X86: Fix the ordering of special physical address ranges. 2008-10-12 14:01:06 -07:00
Gabe Black
557bde43c3 X86: Make APICs communicate through the memory system. 2008-10-12 13:28:54 -07:00
Gabe Black
42ebebf99a X86: Make the local APIC accessible through the memory system directly, and make the timer work. 2008-10-12 11:08:00 -07:00
Gabe Black
d9f9c967fb Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
Gabe Black
c4f1cc3b48 CPU: Eliminate the get_vec function. 2008-10-12 08:24:09 -07:00
Gabe Black
0c3848732e CPU: Add a getInterruptController function 2008-10-11 16:13:58 -07:00
Gabe Black
f621b7b81f CPU: Eliminate the simPalCheck funciton. 2008-10-11 12:17:24 -07:00