Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
--HG--
extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.
--HG--
extra : convert_revision : 17bf9ddae6bc2069e43b076f8f83c4e54fb7966c
There is a fundemental flaw in how unaligned accesses are supported, but this
is still an improvement.
--HG--
extra : convert_revision : 1c20b524ac24cd4a812c876b067495ee6a7ae29f
Merge was returning the value to merge in, not the actual result of the merge.
--HG--
extra : convert_revision : 230b4b5064037d099ae7859edabdf5be84603849
These functions take care of calling the thread contexts read and write functions with the right sized data type, and handle unaligned accesses.
--HG--
extra : convert_revision : b4b59ab2b22559333035185946bae3eab316c879
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
--HG--
extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
--HG--
extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
