Add in support for condition code flags.
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented. --HG-- extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
This commit is contained in:
Gabe Black
parent
cf846d5205
commit
a6757095c3
3 changed files with 309 additions and 87 deletions
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@ -56,10 +56,109 @@
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*/
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#include "arch/x86/insts/microregop.hh"
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#include "arch/x86/miscregs.hh"
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#include "base/condcodes.hh"
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#include <string>
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namespace X86ISA
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{
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uint64_t RegOpBase::genFlags(uint64_t oldFlags, uint64_t flagMask,
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uint64_t _dest, uint64_t _src1, uint64_t _src2) const
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{
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uint64_t flags = oldFlags & ~flagMask;
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if(flagMask & CFBit && findCarry(dataSize, _dest, _src1, _src2))
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flags |= CFBit;
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if(flagMask & PFBit && findParity(dataSize, _dest))
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flags |= PFBit;
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if(flagMask & ECFBit && findCarry(dataSize, _dest, _src1, _src2))
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flags |= ECFBit;
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if(flagMask & AFBit && findCarry(4, _dest, _src1, _src2))
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flags |= AFBit;
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if(flagMask & EZFBit && findZero(dataSize, _dest))
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flags |= EZFBit;
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if(flagMask & ZFBit && findZero(dataSize, _dest))
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flags |= ZFBit;
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if(flagMask & SFBit && findNegative(dataSize, _dest))
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flags |= SFBit;
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if(flagMask & OFBit && findOverflow(dataSize, _dest, _src1, _src2))
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flags |= OFBit;
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return flags;
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}
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bool RegOpBase::checkCondition(uint64_t flags) const
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{
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CCFlagBits ccflags = flags;
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switch(ext)
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{
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case ConditionTests::True:
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return true;
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case ConditionTests::ECF:
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return ccflags.ECF;
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case ConditionTests::EZF:
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return ccflags.EZF;
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case ConditionTests::SZnZF:
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return !(!ccflags.EZF & ccflags.ZF);
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case ConditionTests::MSTRZ:
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panic("This condition is not implemented!");
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case ConditionTests::STRZ:
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panic("This condition is not implemented!");
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case ConditionTests::MSTRC:
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panic("This condition is not implemented!");
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case ConditionTests::STRZnZF:
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panic("This condition is not implemented!");
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case ConditionTests::OF:
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return ccflags.OF;
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case ConditionTests::CF:
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return ccflags.CF;
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case ConditionTests::ZF:
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return ccflags.ZF;
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case ConditionTests::CvZF:
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return ccflags.CF | ccflags.ZF;
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case ConditionTests::SF:
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return ccflags.SF;
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case ConditionTests::PF:
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return ccflags.PF;
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case ConditionTests::SxOF:
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return ccflags.SF ^ ccflags.OF;
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case ConditionTests::SxOvZF:
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return ccflags.SF ^ ccflags.OF | ccflags.ZF;
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case ConditionTests::False:
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return false;
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case ConditionTests::NotECF:
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return !ccflags.ECF;
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case ConditionTests::NotEZF:
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return !ccflags.EZF;
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case ConditionTests::NotSZnZF:
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return !ccflags.EZF & ccflags.ZF;
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case ConditionTests::NotMSTRZ:
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panic("This condition is not implemented!");
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case ConditionTests::NotSTRZ:
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panic("This condition is not implemented!");
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case ConditionTests::NotMSTRC:
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panic("This condition is not implemented!");
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case ConditionTests::NotSTRZnZF:
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panic("This condition is not implemented!");
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case ConditionTests::NotOF:
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return !ccflags.OF;
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case ConditionTests::NotCF:
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return !ccflags.CF;
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case ConditionTests::NotZF:
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return !ccflags.ZF;
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case ConditionTests::NotCvZF:
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return !(ccflags.CF | ccflags.ZF);
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case ConditionTests::NotSF:
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return !ccflags.SF;
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case ConditionTests::NotPF:
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return !ccflags.PF;
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case ConditionTests::NotSxOF:
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return !(ccflags.SF ^ ccflags.OF);
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case ConditionTests::NotSxOvZF:
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return !(ccflags.SF ^ ccflags.OF | ccflags.ZF);
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}
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panic("Unknown condition: %d\n", ext);
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return true;
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}
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std::string RegOp::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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@ -62,18 +62,84 @@
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namespace X86ISA
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{
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namespace ConditionTests
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{
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enum CondTest {
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True,
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NotFalse = True,
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ECF,
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EZF,
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SZnZF,
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MSTRZ,
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STRZ,
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MSTRC,
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STRZnZF,
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OF,
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CF,
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ZF,
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CvZF,
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SF,
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PF,
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SxOF,
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SxOvZF,
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False,
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NotTrue = False,
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NotECF,
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NotEZF,
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NotSZnZF,
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NotMSTRZ,
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NotSTRZ,
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NotMSTRC,
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NotSTRZnZF,
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NotOF,
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NotCF,
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NotZF,
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NotCvZF,
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NotSF,
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NotPF,
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NotSxOF,
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NotSxOvZF
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};
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}
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/**
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* Base classes for RegOps which provides a generateDisassembly method.
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*/
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class RegOp : public X86MicroopBase
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class RegOpBase : public X86MicroopBase
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{
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protected:
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const RegIndex src1;
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const RegIndex src2;
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const RegIndex dest;
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const bool setStatus;
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const uint8_t dataSize;
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const uint8_t ext;
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const uint16_t ext;
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// Constructor
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RegOpBase(ExtMachInst _machInst,
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const char *mnem, const char *_instMnem,
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bool isMicro, bool isDelayed,
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bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext,
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OpClass __opClass) :
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X86MicroopBase(_machInst, mnem, _instMnem,
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isMicro, isDelayed, isFirst, isLast,
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__opClass),
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src1(_src1), dest(_dest),
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dataSize(_dataSize), ext(_ext)
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{
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}
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//Figure out what the condition code flags should be.
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uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask,
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uint64_t _dest, uint64_t _src1, uint64_t _src2) const;
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bool checkCondition(uint64_t flags) const;
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};
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class RegOp : public RegOpBase
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{
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protected:
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const RegIndex src2;
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// Constructor
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RegOp(ExtMachInst _machInst,
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@ -81,13 +147,13 @@ namespace X86ISA
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bool isMicro, bool isDelayed,
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bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext,
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uint8_t _dataSize, uint16_t _ext,
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OpClass __opClass) :
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X86MicroopBase(_machInst, mnem, _instMnem,
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RegOpBase(_machInst, mnem, _instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _dest, _dataSize, _ext,
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__opClass),
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src1(_src1), src2(_src2), dest(_dest),
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setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
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src2(_src2)
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{
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}
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@ -95,15 +161,10 @@ namespace X86ISA
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const SymbolTable *symtab) const;
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};
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class RegOpImm : public X86MicroopBase
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class RegOpImm : public RegOpBase
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{
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protected:
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const RegIndex src1;
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const uint8_t imm8;
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const RegIndex dest;
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const bool setStatus;
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const uint8_t dataSize;
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const uint8_t ext;
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// Constructor
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RegOpImm(ExtMachInst _machInst,
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@ -111,13 +172,13 @@ namespace X86ISA
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bool isMicro, bool isDelayed,
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bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext,
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uint8_t _dataSize, uint16_t _ext,
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OpClass __opClass) :
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X86MicroopBase(_machInst, mnem, _instMnem,
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RegOpBase(_machInst, mnem, _instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _dest, _dataSize, _ext,
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__opClass),
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src1(_src1), imm8(_imm8), dest(_dest),
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setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
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imm8(_imm8)
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{
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}
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@ -67,8 +67,12 @@ def template MicroRegOpExecute {{
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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%(flag_code)s;
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if(%(cond_check)s)
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{
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%(code)s;
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%(flag_code)s;
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}
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//Write the resulting state to the execution context
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if(fault == NoFault)
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@ -87,8 +91,12 @@ def template MicroRegOpImmExecute {{
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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%(flag_code)s;
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if(%(cond_check)s)
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{
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%(code)s;
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%(flag_code)s;
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}
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//Write the resulting state to the execution context
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if(fault == NoFault)
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@ -110,12 +118,12 @@ def template MicroRegOpDeclare {{
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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uint8_t _dataSize, uint8_t _ext);
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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uint8_t _dataSize, uint8_t _ext);
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%(BasicExecDeclare)s
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};
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@ -133,12 +141,12 @@ def template MicroRegOpImmDeclare {{
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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uint8_t _dataSize, uint8_t _ext);
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%(class_name)sImm(ExtMachInst _machInst,
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const char * instMnem,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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uint8_t _dataSize, uint8_t _ext);
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%(BasicExecDeclare)s
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};
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@ -154,10 +162,10 @@ def template MicroRegOpConstructor {{
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inline %(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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false, false, false, false,
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_src1, _src2, _dest, _setStatus, _dataSize, _ext,
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_src1, _src2, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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@ -167,10 +175,10 @@ def template MicroRegOpConstructor {{
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ExtMachInst machInst, const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _src2, _dest, _setStatus, _dataSize, _ext,
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_src1, _src2, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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@ -187,10 +195,10 @@ def template MicroRegOpImmConstructor {{
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inline %(class_name)sImm::%(class_name)sImm(
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ExtMachInst machInst, const char * instMnem,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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false, false, false, false,
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_src1, _imm8, _dest, _setStatus, _dataSize, _ext,
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_src1, _imm8, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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@ -200,10 +208,10 @@ def template MicroRegOpImmConstructor {{
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ExtMachInst machInst, const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _imm8, _dest, _setStatus, _dataSize, _ext,
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_src1, _imm8, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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@ -211,46 +219,74 @@ def template MicroRegOpImmConstructor {{
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}};
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let {{
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class X86MicroMeta(type):
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def __new__(mcls, name, bases, dict):
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abstract = False
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if "abstract" in dict:
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abstract = dict['abstract']
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del dict['abstract']
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cls = type.__new__(mcls, name, bases, dict)
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if not abstract:
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allClasses[name] = cls
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return cls
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class XXX86Microop(object):
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__metaclass__ = X86MicroMeta
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abstract = True
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class RegOp(X86Microop):
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def __init__(self, dest, src1, src2, setStatus):
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abstract = True
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def __init__(self, dest, src1, src2, flags):
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self.dest = dest
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self.src1 = src1
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self.src2 = src2
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self.setStatus = setStatus
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self.flags = flags
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self.dataSize = "env.dataSize"
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self.ext = 0
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if flags is None:
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self.ext = 0
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else:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.ext = " | ".join(flags)
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self.className += "Flags"
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(src2)s, %(dest)s,
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%(setStatus)s, %(dataSize)s, %(ext)s)''' % {
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "src2" : self.src2,
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"dest" : self.dest,
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"setStatus" : self.cppBool(self.setStatus),
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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class RegOpImm(X86Microop):
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def __init__(self, dest, src1, imm8, setStatus):
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abstract = True
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def __init__(self, dest, src1, imm8, flags):
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self.dest = dest
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self.src1 = src1
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self.imm8 = imm8
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self.setStatus = setStatus
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self.flags = flags
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self.dataSize = "env.dataSize"
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self.ext = 0
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if flags is None:
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self.ext = 0
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else:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.ext = " | ".join(flags)
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self.className += "Flags"
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(imm8)s, %(dest)s,
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%(setStatus)s, %(dataSize)s, %(ext)s)''' % {
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "imm8" : self.imm8,
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"dest" : self.dest,
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"setStatus" : self.cppBool(self.setStatus),
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"dataSize" : self.dataSize,
|
||||
"ext" : self.ext}
|
||||
return allocator
|
||||
|
|
@ -264,7 +300,8 @@ let {{
|
|||
decoder_output = ""
|
||||
exec_output = ""
|
||||
|
||||
def setUpMicroRegOp(name, Name, base, code, child, flagCode):
|
||||
# A function which builds the C++ classes that implement the microops
|
||||
def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck):
|
||||
global header_output
|
||||
global decoder_output
|
||||
global exec_output
|
||||
|
|
@ -272,14 +309,20 @@ let {{
|
|||
|
||||
iop = InstObjParams(name, Name, base,
|
||||
{"code" : code,
|
||||
"flag_code" : flagCode})
|
||||
"flag_code" : flagCode,
|
||||
"cond_check" : condCheck})
|
||||
header_output += MicroRegOpDeclare.subst(iop)
|
||||
decoder_output += MicroRegOpConstructor.subst(iop)
|
||||
exec_output += MicroRegOpExecute.subst(iop)
|
||||
|
||||
microopClasses[name] = child
|
||||
|
||||
def defineMicroRegOp(mnemonic, code, flagCode):
|
||||
checkCCFlagBits = "checkCondition(ccFlagBits)"
|
||||
genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);"
|
||||
|
||||
|
||||
# This creates a python representations of a microop which are a cross
|
||||
# product of reg/immediate and flag/no flag versions.
|
||||
def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False):
|
||||
Name = mnemonic
|
||||
name = mnemonic.lower()
|
||||
|
||||
|
|
@ -290,35 +333,47 @@ let {{
|
|||
regCode = matcher.sub("SrcReg2", code)
|
||||
immCode = matcher.sub("imm8", code)
|
||||
|
||||
# Build the all register version of this micro op
|
||||
if not cc:
|
||||
flagCode = genCCFlagBits % secondSrc
|
||||
condCode = "true"
|
||||
else:
|
||||
flagCode = ""
|
||||
condCode = checkCCFlagBits
|
||||
|
||||
regFlagCode = matcher.sub("SrcReg2", flagCode)
|
||||
immFlagCode = matcher.sub("imm8", flagCode)
|
||||
|
||||
class RegOpChild(RegOp):
|
||||
def __init__(self, dest, src1, src2, setStatus=False):
|
||||
super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
mnemonic = name
|
||||
className = Name
|
||||
def __init__(self, dest, src1, src2, flags=None):
|
||||
super(RegOpChild, self).__init__(dest, src1, src2, flags)
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOp", \
|
||||
regCode, RegOpChild, flagCode);
|
||||
microopClasses[name] = RegOpChild
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
|
||||
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode);
|
||||
|
||||
# Build the immediate version of this micro op
|
||||
class RegOpChildImm(RegOpImm):
|
||||
def __init__(self, dest, src1, src2, setStatus=False):
|
||||
super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
|
||||
self.className = Name + "Imm"
|
||||
self.mnemonic = name + "i"
|
||||
mnemonic = name + 'i'
|
||||
className = Name + 'Imm'
|
||||
def __init__(self, dest, src1, src2, flags=None):
|
||||
super(RegOpChildImm, self).__init__(dest, src1, src2, flags)
|
||||
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
|
||||
immCode, RegOpChildImm, flagCode);
|
||||
microopClasses[name + 'i'] = RegOpChildImm
|
||||
|
||||
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
|
||||
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
|
||||
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
|
||||
defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
|
||||
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
|
||||
defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
|
||||
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
|
||||
defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
|
||||
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
|
||||
setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode);
|
||||
|
||||
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
|
||||
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
|
||||
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
|
||||
defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
|
||||
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
|
||||
defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
|
||||
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
|
||||
defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2')
|
||||
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True)
|
||||
|
||||
# This has it's own function because Wr ops have implicit destinations
|
||||
def defineMicroRegOpWr(mnemonic, code):
|
||||
|
|
@ -332,24 +387,27 @@ let {{
|
|||
regCode = matcher.sub("SrcReg2", code)
|
||||
immCode = matcher.sub("imm8", code)
|
||||
|
||||
# Build the all register version of this micro op
|
||||
class RegOpChild(RegOp):
|
||||
def __init__(self, src1, src2):
|
||||
super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
mnemonic = name
|
||||
className = Name
|
||||
def __init__(self, src1, src2, flags=None):
|
||||
super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags)
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
|
||||
microopClasses[name] = RegOpChild
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
|
||||
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits);
|
||||
|
||||
# Build the immediate version of this micro op
|
||||
class RegOpChildImm(RegOpImm):
|
||||
mnemonic = name
|
||||
className = Name
|
||||
def __init__(self, src1, src2):
|
||||
super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
|
||||
self.className = Name + "Imm"
|
||||
self.mnemonic = name + "i"
|
||||
super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None)
|
||||
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
|
||||
immCode, RegOpChildImm, "");
|
||||
microopClasses[name + 'i'] = RegOpChildImm
|
||||
|
||||
setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
|
||||
setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits);
|
||||
|
||||
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
|
||||
|
||||
|
|
@ -360,11 +418,13 @@ let {{
|
|||
|
||||
class RegOpChild(RegOp):
|
||||
def __init__(self, dest, src1 = "NUM_INTREGS"):
|
||||
super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
|
||||
super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
|
||||
microopClasses[name] = RegOpChild
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true");
|
||||
|
||||
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
|
||||
|
||||
|
|
@ -374,11 +434,13 @@ let {{
|
|||
|
||||
class RegOpChild(RegOpImm):
|
||||
def __init__(self, dest, src1, src2):
|
||||
super(RegOpChild, self).__init__(dest, src1, src2, False)
|
||||
super(RegOpChild, self).__init__(dest, src1, src2, None)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
|
||||
microopClasses[name] = RegOpChild
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true");
|
||||
|
||||
defineMicroRegOpImm('Sext', '''
|
||||
IntReg val = SrcReg1;
|
||||
|
|
|
|||
Loading…
Reference in a new issue