Add in operand which holds the condition code bits of the flag register.

--HG-- extra : convert_revision : 416052f41fccc8286b3bdbe8d559512a761224f2
2007-07-17 15:28:48 -07:00 · 2007-07-17 15:28:48 -07:00 · cf846d5205
parent bbf7163dd9
commit cf846d5205
1 changed files with 1 additions and 0 deletions
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@ -103,5 +103,6 @@ def operands {{
        'Index':         ('IntReg', 'uqw', 'index', 'IsInteger', 5),
        'Data':          ('IntReg', 'uqw', 'data', 'IsInteger', 6),
        'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
+        'ccFlagBits':       ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
        'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};