See configs/test.py for test config (using simple
binary in my home directory on zizzer).
base/chunk_generator.hh:
Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
Fix roundDown to take integer alignments.
cpu/base.cc:
Register exec contexts regardless of state (not sure why
this check was in here in the first place).
mem/physical.cc:
Add breaks to switch.
python/m5/objects/BaseCPU.py:
Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
HierParams is gone.
python/m5/objects/PhysicalMemory.py:
mmu param is full-system only.
sim/process.cc:
Stack mapping request must be page-aligned and page-sized.
Don't delete objFile object in create since we are counting
on it being around for startup().
--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
arch/sparc/linux_process.cc:
Began modifying this file for sparc, and replaced the alpha syscall numbers with the sparc ones.
arch/sparc/linux_process.hh:
Begain modifying this file for sparc.
--HG--
extra : convert_revision : b1ed8ac50a35591521c5feaf1ea9c4b8ccc26dc8
arch/alpha/ev5.cc:
Commented out the intr_post function since it's not used. If this really -is- needed, it should be moved into the fault class.
arch/alpha/faults.cc:
arch/alpha/faults.hh:
Moved the fault invocation code into the fault class fully, and got rid of the need for isA.
cpu/exec_context.cc:
cpu/exec_context.hh:
Removed the trap function from the ExecContext. The faults will execute normally in full system mode, but always panic in syscall emulation mode.
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Changed the execution context executing a fault to a fault executing on the execution context.
sim/faults.cc:
If not in full system mode, trying to invoke a fault causes a panic.
sim/faults.hh:
Removed the isA function.
--HG--
extra : convert_revision : 894dc8f0755c8efc4b7ef5a09fb2cf7373042395
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Formatting & doxygen.
arch/sparc/linux_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit, times and rt_sigaction.
Should eventually provide a function for times.
arch/sparc/linux_process.cc:
Fixes for Linux emulation:
- stat struct alignment
- osf_{get,set}sysinfo return values
- additional syscall numbers
- initialize $r0 to 0
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Updated Copyright
arch/sparc/linux_process.cc:
Alphabetize includes.
arch/sparc/linux_process.cc:
Changed all syscalls to use syscall return object
arch/sparc/linux_process.cc:
Removed unecessary constructor call at each return.
arch/sparc/linux_process.cc:
Rename sim/universe.{cc,hh} to root.{cc,hh}.
arch/sparc/linux_process.cc:
shuffle files around for new directory structure
arch/sparc/linux_process.cc:
Remove RCS Id string
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
Update copyright dates and author list
arch/sparc/linux_process.hh:
remove $Id$ string
arch/sparc/linux_process.cc:
Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).
arch/sparc/linux_process.cc:
Added the endianness namespace. This may change.
arch/sparc/linux_process.cc:
Replaced the namespace declaration with including arch/alpha/isa_traits.hh
arch/sparc/linux_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
arch/sparc/linux_process.cc:
Add endian conversions to fstat
arch/sparc/linux_process.cc:
fix #if. I wonder why my compiler had no issues
arch/sparc/linux_process.cc:
add endian conversions for fstat functions
arch/sparc/linux_process.cc:
move architecture independent code into kern/linux/linux.(hh|cc)
arch/sparc/linux_process.hh:
Add getDesc function
arch/sparc/linux_process.cc:
Added using directive for AlphaISA namespace
arch/sparc/linux_process.cc:
Add pipeFunc.
arch/alpha/linux_process.cc:
Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
arch/sparc/linux_process.cc:
bk cp ../alpha/linux_process.cc linux_process.cc
arch/sparc/linux_process.hh:
bk cp ../alpha/linux_process.hh linux_process.hh
--HG--
extra : convert_revision : a8eca1c5f848383263a2326b0e3cde4bcd85f14b
This changeset removes a check that prevents quiescing when an
interrupt is pending. *** You should only call quiesce if that
isn't a problem. ***
arch/alpha/isa/decoder.isa:
sim/pseudo_inst.cc:
sim/pseudo_inst.hh:
Add quiesceNs, quiesceCycles, quisceTime and m5panic pseudo ops.
These quiesce for a number of ns, cycles, report how long
we were quiesced for, and panic the simulator respectively.
The latter is added to the panic() function in the console and linux
kernel instead of executing an infinite loop until someone notices.
cpu/exec_context.cc:
cpu/exec_context.hh:
Add a quiesce end event to the execution contexted which upon
executing wakes up a CPU for quiesceCycles/quiesceNs.
util/m5/Makefile:
Make the makefile more reasonable
util/m5/m5.c:
update the m5op executable to use the files from the linux tree
util/m5/m5op.S:
update m5op.S from linux tree
util/m5/m5op.h:
update m5op.h from linux tree
--HG--
rename : util/m5/m5op.s => util/m5/m5op.S
extra : convert_revision : 3be18525e811405b112e33f24a8c4e772d15462d
arch/alpha/ev5.cc:
Changed c style casts of Faults to dynamic_casts
arch/alpha/faults.cc:
AlphaFault is now an abstract class.
arch/alpha/faults.hh:
AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes.
cpu/o3/alpha_cpu_impl.hh:
Changed a c style cast to a dynamic_cast for a Fault
sim/faults.hh:
All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults.
--HG--
extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc
SConscript:
Add Back memory to be built
mem/physical.hh:
Fix function declerations
python/m5/objects/BaseCPU.py:
Remove IL1 and DL1 params from the cpu object
--HG--
extra : convert_revision : 2f285dc626bc8d84d095def68e986fe7e6f3d8e9
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).
arch/alpha/alpha_memory.cc:
Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes.
The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
Change access to the IPR to go through the XC.
arch/isa_parser.py:
Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
Change accesses to the IPRs to go through the miscRegs.
For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
Remove old misc reg accessors.
cpu/o3/cpu.cc:
Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
Change accesses to the misc regs.
cpu/o3/regfile.hh:
Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
Have accesses to the misc regs use the new access methods.
--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
SConscript:
Changed all of the "targetarch" files to be "arch" files
arch/SConscript:
Added all of the remaining targetarch files to isa_switch_hdrs
--HG--
extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
kern/kernel_stats.cc:
Replaced targetarch with arch/alpha, since osfpal.hh is not a targetarched file.
--HG--
extra : convert_revision : 24a25f27e5912cb949568cf5fd0ab856771ba0d1
arch/alpha/ev5.cc:
cpu/simple/cpu.cc:
Changed from the isA templated function to isMachineCheckFault and isAlignmentFault
sim/faults.hh:
Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class.
--HG--
extra : convert_revision : 3bf3a4369bc24a039648ee4f2a9c1663362ff2e2
arch/alpha/alpha_memory.cc:
cpu/base_dyn_inst.cc:
dev/alpha_console.cc:
dev/pcidev.hh:
dev/sinic.cc:
MachineCheckFaults are now generated by the ISA, rather than being created directly.
--HG--
extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
dev/pktfifo.cc:
add support for copying arbitrary data out of a
packet fifo
dev/pktfifo.hh:
add support for copying arbitrary data out of a
packet fifo.
Add functions to determine where in the fifo a
particular packet is
--HG--
extra : convert_revision : f8ddc994ce8577f29af0de3fa418a01e4e2cb0f1
util/stats/barchart.py:
clean up some of lisa's messy code
remove trailing whitespace while I'm at it.
--HG--
extra : convert_revision : f2fe6777fb4b458fa1d5b5b743f6274014c229ad
util/stats/chart.py:
add a bool config option for determining
if the legend is inside or outside the figure
--HG--
extra : convert_revision : e862d1832a0cc3c1837758cc247bc77c0a02ec12
util/stats/barchart.py:
Add support for error bars
util/stats/barchart.py:
add support to choose between a legend inside or
outside the figure.
--HG--
extra : convert_revision : 14273e385c106bf27a2013991f9f34ca6551b96c
util/stats/barchart.py:
If there are fewer than 5 colors, pick from a subset of
5 so there is more consistency in colors between graphs
--HG--
extra : convert_revision : 6cf64c2f8ed81e714e24a3ebe5a7a60ca168b231
CPU_MODELS parameter changes.
arch/SConscript:
Fix typo in comment.
cpu/SConscript:
Convert exec signature generator to Action so we can add dependency
on CPU_MODELS environment var.
Print nicer string while we're at it.
Also add some comments.
--HG--
extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
into ewok.(none):/home/gblack/m5/multiarch
SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
Hand merged
--HG--
extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
2) make subticks vertical so they can be longer
3) make inner and outer axes farther apart to make room for subtick's vertical labels
--HG--
extra : convert_revision : 91a1aab3f1078921edd53428e6712744210c9f1b
